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文件名称:sdram

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    760.84kb
  • 已下载：
    0次
  • 提 供 者：
    军***
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

程序说明:

本次实验控制开发板上面的SDRAM完成读写功能。

先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。

part1是使用Modelsim仿真的工程

part2是在开发斑上面验证的工程

目录说明:

part1:

part1_32是4m32SDRAM的仿真工程

part1_16是4m16SDRAM的仿真工程

\model文件夹里面是仿真模型

\rtl文件夹里面是源文件

\sim文件夹里面是仿真工程

\test_bench文件夹里面是测试文件

\wave文件夹里面是仿真波形

-Procedure Note: In this experiment, control development board to complete the above SDRAM read and write capabilities. SDRAM write data inside first and then read out the data to compare, if you do not match on the adoption of LED variable light display, if agreed, LED does not light. part1 is to use Modelsim simulation project part2 the top spot verification in the development of the project directory Descr iption: part1: part1_32 is 4m32SDRAM simulation project part1_16 is 4m16SDRAM simulation works \ model folder, which is a simulation model \ rtl folder, which is the source file \ sim is a simulation project inside the folder \ test_bench folder which is a test file \ wave inside the folder is a simulation waveform
相关搜索： sdram vhdl sdram rtl

(系统自动生成,下载前可以参看下载内容)

下载文件列表

s16_sdram/introduce.txt
s16_sdram/part1/part1_32/model/mt48lc2m32b2.v
s16_sdram/part1/part1_32/rtl/Command.v
s16_sdram/part1/part1_32/rtl/control_interface.v
s16_sdram/part1/part1_32/rtl/Params.v
s16_sdram/part1/part1_32/rtl/sdr_data_path.v
s16_sdram/part1/part1_32/rtl/sdr_sdram.v
s16_sdram/part1/part1_32/sim/Command.v
s16_sdram/part1/part1_32/sim/control_interface.v
s16_sdram/part1/part1_32/sim/mt48lc2m32b2.v
s16_sdram/part1/part1_32/sim/Params.v
s16_sdram/part1/part1_32/sim/sd32try.cr.mti
s16_sdram/part1/part1_32/sim/sd32try.mpf
s16_sdram/part1/part1_32/sim/sdram_test_tb.v
s16_sdram/part1/part1_32/sim/sdr_data_path.v
s16_sdram/part1/part1_32/sim/sdr_sdram.v
s16_sdram/part1/part1_32/sim/sdtry.cr.mti
s16_sdram/part1/part1_32/sim/vsim.wlf
s16_sdram/part1/part1_32/sim/wave.do
s16_sdram/part1/part1_32/sim/work/command/verilog.asm
s16_sdram/part1/part1_32/sim/work/command/_primary.dat
s16_sdram/part1/part1_32/sim/work/command/_primary.vhd
s16_sdram/part1/part1_32/sim/work/control_interface/verilog.asm
s16_sdram/part1/part1_32/sim/work/control_interface/_primary.dat
s16_sdram/part1/part1_32/sim/work/control_interface/_primary.vhd
s16_sdram/part1/part1_32/sim/work/mt48lc2m32b2/verilog.asm
s16_sdram/part1/part1_32/sim/work/mt48lc2m32b2/_primary.dat
s16_sdram/part1/part1_32/sim/work/mt48lc2m32b2/_primary.vhd
s16_sdram/part1/part1_32/sim/work/sdram_test_tb/verilog.asm
s16_sdram/part1/part1_32/sim/work/sdram_test_tb/_primary.dat
s16_sdram/part1/part1_32/sim/work/sdram_test_tb/_primary.vhd
s16_sdram/part1/part1_32/sim/work/sdr_data_path/verilog.asm
s16_sdram/part1/part1_32/sim/work/sdr_data_path/_primary.dat
s16_sdram/part1/part1_32/sim/work/sdr_data_path/_primary.vhd
s16_sdram/part1/part1_32/sim/work/sdr_sdram/verilog.asm
s16_sdram/part1/part1_32/sim/work/sdr_sdram/_primary.dat
s16_sdram/part1/part1_32/sim/work/sdr_sdram/_primary.vhd
s16_sdram/part1/part1_32/sim/work/_info
s16_sdram/part1/part1_32/test_bench/sdram_test_tb.v
s16_sdram/part1/part1_32/wave/32wave.bmp
s16_sdram/part1/part2_16/model/mt48lc8m16a2.v
s16_sdram/part1/part2_16/rtl/Command.v
s16_sdram/part1/part2_16/rtl/control_interface.v
s16_sdram/part1/part2_16/rtl/Params.v
s16_sdram/part1/part2_16/rtl/sdr_data_path.v
s16_sdram/part1/part2_16/rtl/sdr_sdram.v
s16_sdram/part1/part2_16/sim/Command.v
s16_sdram/part1/part2_16/sim/control_interface.v
s16_sdram/part1/part2_16/sim/mt48lc8m16a2.v
s16_sdram/part1/part2_16/sim/Params.v
s16_sdram/part1/part2_16/sim/sdram_test_tb.v
s16_sdram/part1/part2_16/sim/sdr_data_path.v
s16_sdram/part1/part2_16/sim/sdr_sdram.v
s16_sdram/part1/part2_16/sim/sdtest.cr.mti
s16_sdram/part1/part2_16/sim/sdtest.mpf
s16_sdram/part1/part2_16/sim/vish_stacktrace.vstf
s16_sdram/part1/part2_16/sim/vsim.wlf
s16_sdram/part1/part2_16/sim/work/command/verilog.asm
s16_sdram/part1/part2_16/sim/work/command/_primary.dat
s16_sdram/part1/part2_16/sim/work/command/_primary.vhd
s16_sdram/part1/part2_16/sim/work/control_interface/verilog.asm
s16_sdram/part1/part2_16/sim/work/control_interface/_primary.dat
s16_sdram/part1/part2_16/sim/work/control_interface/_primary.vhd
s16_sdram/part1/part2_16/sim/work/mt48lc8m16a2/verilog.asm
s16_sdram/part1/part2_16/sim/work/mt48lc8m16a2/_primary.dat
s16_sdram/part1/part2_16/sim/work/mt48lc8m16a2/_primary.vhd
s16_sdram/part1/part2_16/sim/work/sdram_test/verilog.asm
s16_sdram/part1/part2_16/sim/work/sdram_test/_primary.dat
s16_sdram/part1/part2_16/sim/work/sdram_test/_primary.vhd
s16_sdram/part1/part2_16/sim/work/sdram_test_tb/verilog.asm
s16_sdram/part1/part2_16/sim/work/sdram_test_tb/_primary.dat
s16_sdram/part1/part2_16/sim/work/sdram_test_tb/_primary.vhd
s16_sdram/part1/part2_16/sim/work/sdr_data_path/verilog.asm
s16_sdram/part1/part2_16/sim/work/sdr_data_path/_primary.dat
s16_sdram/part1/part2_16/sim/work/sdr_data_path/_primary.vhd
s16_sdram/part1/part2_16/sim/work/sdr_sdram/verilog.asm
s16_sdram/part1/part2_16/sim/work/sdr_sdram/_primary.dat
s16_sdram/part1/part2_16/sim/work/sdr_sdram/_primary.vhd
s16_sdram/part1/part2_16/sim/work/test/verilog.asm
s16_sdram/part1/part2_16/sim/work/test/_primary.dat
s16_sdram/part1/part2_16/sim/work/test/_primary.vhd
s16_sdram/part1/part2_16/sim/work/test_top/verilog.asm
s16_sdram/part1/part2_16/sim/work/test_top/_primary.dat
s16_sdram/part1/part2_16/sim/work/test_top/_primary.vhd
s16_sdram/part1/part2_16/sim/work/_info
s16_sdram/part1/part2_16/test_bench/sdram_test_tb.v
s16_sdram/part1/part2_16/wave/wave.bmp
s16_sdram/part2/project/bitgen.ut
s16_sdram/part2/project/Project.dhp
s16_sdram/part2/project/project.ise
s16_sdram/part2/project/project.ise_ISE_Backup
s16_sdram/part2/project/test.bgn
s16_sdram/part2/project/test.bit
s16_sdram/part2/project/test.bld
s16_sdram/part2/project/test.cmd_log
s16_sdram/part2/project/test.drc
s16_sdram/part2/project/test.lfp
s16_sdram/part2/project/test.lso
s16_sdram/part2/project/test.mrp
s16_sdram/part2/project/test.nc1
s16_sdram/part2/project/test.ncd
s16_sdram/part2/project/test.ngc
s16_sdram/part2/project/test.ngd
s16_sdram/part2/project/test.ngm
s16_sdram/part2/project/test.ngr
s16_sdram/part2/project/test.pad
s16_sdram/part2/project/test.pad_txt
s16_sdram/part2

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