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文件名称:dual_core
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- 上传时间：2012-11-16
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文件大小：261.08kb
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This example application shows you how to use Real-Time Workshop Embedded Coder to target a dual core Blackfin microprocessor. The complete build is managed by a template makefile and control over the memory regions is provided by custom storage classes. The example imposes a top level architecture on the model to define the split of model code between the two cores. This document describes a complete run-through of the model from Simulink simulation to code simulation using VisualDSP. I think it will take about 1 hour to go through the example once you have VisualDSP installed.
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下载文件列表
@Blackfin/
@Blackfin/@CustomRTWInfo_Parameter/
@Blackfin/@CustomRTWInfo_Parameter/Blackfin_CustomRTWInfo_Parameter_Constructor.p
@Blackfin/@CustomRTWInfo_Parameter/CustomRTWInfo_Parameter.p
@Blackfin/@CustomRTWInfo_Parameter/CustomStorageClassListener.p
@Blackfin/@CustomRTWInfo_Parameter/schema.p
@Blackfin/@CustomRTWInfo_Signal/
@Blackfin/@CustomRTWInfo_Signal/Blackfin_CustomRTWInfo_Signal_Constructor.p
@Blackfin/@CustomRTWInfo_Signal/CustomRTWInfo_Signal.p
@Blackfin/@CustomRTWInfo_Signal/CustomStorageClassListener.p
@Blackfin/@CustomRTWInfo_Signal/schema.p
@Blackfin/@Dual/
@Blackfin/@Dual/Blackfin_Dual_Constructor.p
@Blackfin/@Dual/Dual.p
@Blackfin/@Dual/schema.p
@Blackfin/csc_registration.m
@Blackfin/packagedefn.mat
@Blackfin/schema.p
@Blackfin/tlc/
@Blackfin/tlc/BF561_FAST_L1_RAM.tlc
@Blackfin/tlc/BF561_SHARED_RAM.tlc
dsp_dual.tlc
dsp_dual.tmf
dual_basiccrt.doj
dual_core.mdl
dual_core_variables.m
expected_result.jpg
expected_result2.jpg
license.txt
readme.html
result.jpg
short_dos.jpg
toplevel.jpg
@Blackfin/@CustomRTWInfo_Parameter/
@Blackfin/@CustomRTWInfo_Parameter/Blackfin_CustomRTWInfo_Parameter_Constructor.p
@Blackfin/@CustomRTWInfo_Parameter/CustomRTWInfo_Parameter.p
@Blackfin/@CustomRTWInfo_Parameter/CustomStorageClassListener.p
@Blackfin/@CustomRTWInfo_Parameter/schema.p
@Blackfin/@CustomRTWInfo_Signal/
@Blackfin/@CustomRTWInfo_Signal/Blackfin_CustomRTWInfo_Signal_Constructor.p
@Blackfin/@CustomRTWInfo_Signal/CustomRTWInfo_Signal.p
@Blackfin/@CustomRTWInfo_Signal/CustomStorageClassListener.p
@Blackfin/@CustomRTWInfo_Signal/schema.p
@Blackfin/@Dual/
@Blackfin/@Dual/Blackfin_Dual_Constructor.p
@Blackfin/@Dual/Dual.p
@Blackfin/@Dual/schema.p
@Blackfin/csc_registration.m
@Blackfin/packagedefn.mat
@Blackfin/schema.p
@Blackfin/tlc/
@Blackfin/tlc/BF561_FAST_L1_RAM.tlc
@Blackfin/tlc/BF561_SHARED_RAM.tlc
dsp_dual.tlc
dsp_dual.tmf
dual_basiccrt.doj
dual_core.mdl
dual_core_variables.m
expected_result.jpg
expected_result2.jpg
license.txt
readme.html
result.jpg
short_dos.jpg
toplevel.jpg
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