- ics .\\ Info directory .\\delphi\\internet Delphi sample applications (all Delphi versions) .\\cpp\\internet C++Builder sample applications .\\cpp\\internet\\bcb1 C++Builder version 1 projects .\\cpp\\internet\\bcb3 C++Builder version 3 projects .\\cpp\\internet\\bcb4 C++Builder version 4 projects .\\cpp\\internet\\bcb5 C++Builder version 5 projects .\\cpp\\internet\\bcb6 C++Builder version 6 projects .\\delphi\\vc Delphi 1.x files (winsock.pas 16 bits and *.dcr) .\\delphi\\vc32 Delphi (1/2/3/4/5/6/7) and C++Builder (1/3/4/5/6) components .\\Delphi1 Automated build for Delphi 1. Not for beginners. .\\Delphi2 Automated build for Delphi 2. Not for beginners. .\\Delphi3 Automated build for Delphi 3. Not for beginners. .\\bcb1 Automated build for Bcb 1. Not for beginners.
- 该程序是将读到的IC卡卡号转换成韦根26代码进行输出
- 29_delphi_DanJetX_07 Delphi Game Components. Very Good.
- dtrgn For lack of EMD
- AES KU-2 AES ENCRYPTION ALGORITHM
- Desktop 不需要调用函数编写正态分布生成随机数程序(normal distribution generate random numbers)
文件名称:DDRcontrol
介绍说明--下载内容来自于网络,使用问题请自行百度
DDR控制器的设计参考,包含有中文说明文档-DDR controller design for reference, including documentation in Chinese
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_addr_gen_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_backend_fifos_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_backend_rom_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_cmp_rd_data_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_controller_iobs_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_data_gen_16.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_data_path_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_data_path_iobs_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_data_tap_inc.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_data_write_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_ddr_controller_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_idelay_ctrl.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_infrastructure.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_infrastructure_iobs_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_iobs_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_main_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_parameters_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_pattern_compare8.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_RAM_D_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_rd_data_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_rd_data_fifo_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_rd_wr_addr_fifo_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_tap_ctrl_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_tap_logic_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_test_bench_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_top_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_user_interface_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_v4_dm_iob.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_v4_dqs_iob.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_v4_dq_iob.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_wr_data_fifo_16.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器.pdf
DDR SDRAM/DDR SDRAM/DDR SDRAM
DDR SDRAM/DDR SDRAM
DDR SDRAM
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_addr_gen_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_backend_fifos_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_backend_rom_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_cmp_rd_data_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_controller_iobs_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_data_gen_16.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_data_path_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_data_path_iobs_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_data_tap_inc.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_data_write_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_ddr_controller_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_idelay_ctrl.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_infrastructure.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_infrastructure_iobs_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_iobs_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_main_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_parameters_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_pattern_compare8.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_RAM_D_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_rd_data_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_rd_data_fifo_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_rd_wr_addr_fifo_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_tap_ctrl_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_tap_logic_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_test_bench_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_top_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_user_interface_0.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_v4_dm_iob.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_v4_dqs_iob.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_v4_dq_iob.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/mem_interface_top_wr_data_fifo_16.txt
DDR SDRAM/DDR SDRAM/DDR SDRAM/使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器.pdf
DDR SDRAM/DDR SDRAM/DDR SDRAM
DDR SDRAM/DDR SDRAM
DDR SDRAM
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