文件名称:mem-if-rtl
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- 上传时间:2012-11-16
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文件大小:22.23kb
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实现memory的interface,就是memory的接口实现,可以在fpga上进行综合仿真-Achieve the memory of the interface, is the memory of the interface, you can fpga on the integrated simulation
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下载文件列表
rtl/CVS/Entries
rtl/CVS/Entries.Extra
rtl/CVS/Entries.Extra.Old
rtl/CVS/Entries.Old
rtl/CVS/Repository
rtl/CVS/Root
rtl/CVS/Template
rtl/verilog/CVS/Entries
rtl/verilog/CVS/Entries.Extra
rtl/verilog/CVS/Entries.Extra.Old
rtl/verilog/CVS/Entries.Old
rtl/verilog/CVS/Repository
rtl/verilog/CVS/Root
rtl/verilog/CVS/Template
rtl/verilog/mem_if_flash_if.v
rtl/verilog/mem_if_registered_feedback.v
rtl/verilog/mem_if_ro_top.v
rtl/verilog/mem_if_sdramcnt.v
rtl/verilog/mem_if_sdram_defines.v
rtl/verilog/mem_if_sdram_dp.v
rtl/verilog/mem_if_sdram_flash_defines.v
rtl/verilog/mem_if_sdram_top.v
rtl/verilog/mem_if_top.v
rtl/verilog/CVS
rtl/CVS
rtl/verilog
rtl
rtl/CVS/Entries.Extra
rtl/CVS/Entries.Extra.Old
rtl/CVS/Entries.Old
rtl/CVS/Repository
rtl/CVS/Root
rtl/CVS/Template
rtl/verilog/CVS/Entries
rtl/verilog/CVS/Entries.Extra
rtl/verilog/CVS/Entries.Extra.Old
rtl/verilog/CVS/Entries.Old
rtl/verilog/CVS/Repository
rtl/verilog/CVS/Root
rtl/verilog/CVS/Template
rtl/verilog/mem_if_flash_if.v
rtl/verilog/mem_if_registered_feedback.v
rtl/verilog/mem_if_ro_top.v
rtl/verilog/mem_if_sdramcnt.v
rtl/verilog/mem_if_sdram_defines.v
rtl/verilog/mem_if_sdram_dp.v
rtl/verilog/mem_if_sdram_flash_defines.v
rtl/verilog/mem_if_sdram_top.v
rtl/verilog/mem_if_top.v
rtl/verilog/CVS
rtl/CVS
rtl/verilog
rtl
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