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文件名称:microprocessor

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    2012-11-16
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    203.79kb
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一个微处理器的Verilog代码,根据英文书籍《数字设计与架构》中的例子而写,能够运行MIPS指令,能正确执行跳转指令。通过modelsim仿真,含测试代码。-Verilog code for a microprocessor, according to the English book " Digital Design and Architecture" was written in the example, to run MIPS instructions to jump correctly. By modelsim simulation, with test code.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

microprocessor/adder.v
microprocessor/alu.v
microprocessor/controller.v
microprocessor/datapath.v
microprocessor/datapath.v.bak
microprocessor/datapath1.v
microprocessor/dmem.v
microprocessor/equal.v
microprocessor/flop.v
microprocessor/flop2.v
microprocessor/flopr.v
microprocessor/flopr1.v
microprocessor/flopr3.v
microprocessor/flopr4.v
microprocessor/hazardunit.v
microprocessor/hewenjuan.cr.mti
microprocessor/hewenjuan.mpf
microprocessor/imem.v
microprocessor/memfile.dat
microprocessor/microprocessortest.cr.mti
microprocessor/microprocessortest.mpf
microprocessor/mips.v
microprocessor/mips.v.bak
microprocessor/mux2.v
microprocessor/mux3.v
microprocessor/mux3.v.bak
microprocessor/regfile.v
microprocessor/signext.v
microprocessor/sl2.v
microprocessor/testbench.v
microprocessor/testbench.v.bak
microprocessor/test_flop.v
microprocessor/tes_hazardunit.v
microprocessor/top.v
microprocessor/top.v.bak
microprocessor/transcript
microprocessor/vsim.wlf
microprocessor/work/memfile.dat
microprocessor/work/_info
microprocessor/work/top/verilog.asm
microprocessor/work/top/_primary.dat
microprocessor/work/top/_primary.vhd
microprocessor/work/test_hazardunit/verilog.asm
microprocessor/work/test_hazardunit/_primary.dat
microprocessor/work/test_hazardunit/_primary.vhd
microprocessor/work/test_flop/verilog.asm
microprocessor/work/test_flop/_primary.dat
microprocessor/work/test_flop/_primary.vhd
microprocessor/work/testbench/verilog.asm
microprocessor/work/testbench/_primary.dat
microprocessor/work/testbench/_primary.vhd
microprocessor/work/sl2/verilog.asm
microprocessor/work/sl2/_primary.dat
microprocessor/work/sl2/_primary.vhd
microprocessor/work/signext/verilog.asm
microprocessor/work/signext/_primary.dat
microprocessor/work/signext/_primary.vhd
microprocessor/work/regfile/verilog.asm
microprocessor/work/regfile/_primary.dat
microprocessor/work/regfile/_primary.vhd
microprocessor/work/mux3/verilog.asm
microprocessor/work/mux3/_primary.dat
microprocessor/work/mux3/_primary.vhd
microprocessor/work/mux2/verilog.asm
microprocessor/work/mux2/_primary.dat
microprocessor/work/mux2/_primary.vhd
microprocessor/work/mips/verilog.asm
microprocessor/work/mips/_primary.dat
microprocessor/work/mips/_primary.vhd
microprocessor/work/maindec/verilog.asm
microprocessor/work/maindec/_primary.dat
microprocessor/work/maindec/_primary.vhd
microprocessor/work/imem/verilog.asm
microprocessor/work/imem/_primary.dat
microprocessor/work/imem/_primary.vhd
microprocessor/work/hazardunit/verilog.asm
microprocessor/work/hazardunit/_primary.dat
microprocessor/work/hazardunit/_primary.vhd
microprocessor/work/flopr4/verilog.asm
microprocessor/work/flopr4/_primary.dat
microprocessor/work/flopr4/_primary.vhd
microprocessor/work/flopr3/verilog.asm
microprocessor/work/flopr3/_primary.dat
microprocessor/work/flopr3/_primary.vhd
microprocessor/work/flopr2/verilog.asm
microprocessor/work/flopr2/_primary.dat
microprocessor/work/flopr2/_primary.vhd
microprocessor/work/flopr1/verilog.asm
microprocessor/work/flopr1/_primary.dat
microprocessor/work/flopr1/_primary.vhd
microprocessor/work/flopr/verilog.asm
microprocessor/work/flopr/_primary.dat
microprocessor/work/flopr/_primary.vhd
microprocessor/work/flop/verilog.asm
microprocessor/work/flop/_primary.dat
microprocessor/work/flop/_primary.vhd
microprocessor/work/equal/verilog.asm
microprocessor/work/equal/_primary.dat
microprocessor/work/equal/_primary.vhd
microprocessor/work/dmem/verilog.asm
microprocessor/work/dmem/_primary.dat
microprocessor/work/dmem/_primary.vhd
microprocessor/work/datapath/verilog.asm
microprocessor/work/datapath/_primary.dat
microprocessor/work/datapath/_primary.vhd
microprocessor/work/controller/verilog.asm
microprocessor/work/controller/_primary.dat
microprocessor/work/controller/_primary.vhd
microprocessor/work/aludec/verilog.asm
microprocessor/work/aludec/_primary.dat
microprocessor/work/aludec/_primary.vhd
microprocessor/work/alu/verilog.asm
microprocessor/work/alu/_primary.dat
microprocessor/work/alu/_primary.vhd
microprocessor/work/adder/verilog.asm
microprocessor/work/adder/_primary.dat
microprocessor/work/adder/_primary.vhd
microprocessor/work/@c__@modeltech_5_8a_modelsim_lib_@mtest_microprocessor_datapath1_v_$root/verilog.asm
microprocessor/work/@c__@modeltech_5_8a_modelsim_lib_@mtest_microprocessor_datapath1_v_$root/_primary.dat
microprocessor/work/@c__@modeltech_5_8a_modelsim_lib_@mtest_microprocessor_datapath1_v_$root/_primary.vhd
microprocessor/work/top
microprocessor/work/test_hazardunit
microprocessor/work/test_flop
microprocessor/work/testbench
microprocessor/work/sl2
microprocessor/work/signext
microprocessor/work/regfile
microprocessor/work/mux3
microprocessor/work/mux2
microprocessor/work/mips
microprocessor/work/maindec
microprocessor/work/imem
microprocessor/work/hazardunit
microprocessor/work/flopr4
microprocessor/work/flopr3
microprocessor/work/flopr2
microprocessor/work/flopr1
microprocessor/work/flopr
microprocessor/work/flop
microprocessor/work/equal
microprocessor/work/dmem
microprocessor/work/datapath
microprocessor/work/controller
microprocessor/work/aludec
microprocessor/work/alu

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