74hc74.pdf
74hc74/
74hc74/component/
74hc74/constraint/
74hc74/coreconsole/
74hc74/designer/
74hc74/designer/impl1/
74hc74/designer/impl1/designer.log
74hc74/designer/impl1/d_ff.adb
74hc74/designer/impl1/d_ff.dtf/
74hc74/designer/impl1/d_ff.dtf/verify.log
74hc74/designer/impl1/d_ff.ide_des
74hc74/designer/impl1/d_ff.pdb
74hc74/designer/impl1/d_ff.pdb.depends
74hc74/designer/impl1/d_ff.tcl
74hc74/designer/impl1/d_ff_fp/
74hc74/designer/impl1/d_ff_fp/$$FlashPro_07294.L$$
74hc74/designer/impl1/d_ff_fp/d_ff.log
74hc74/designer/impl1/d_ff_fp/d_ff.pro
74hc74/designer/impl1/d_ff_fp/projectData/
74hc74/designer/impl1/d_ff_fp/projectData/d_ff.pdb
74hc74/designer/impl1/simulation/
74hc74/d_ff.prj
74hc74/hdl/
74hc74/hdl/d_ff.v
74hc74/phy_synthesis/
74hc74/simulation/
74hc74/simulation/modelsim.ini
74hc74/simulation/modelsim.ini.sav
74hc74/smartgen/
74hc74/smartgen/smartgen.aws
74hc74/stimulus/
74hc74/synthesis/
74hc74/synthesis/backup/
74hc74/synthesis/backup/d_ff.srr
74hc74/synthesis/coreip/
74hc74/synthesis/d_ff.areasrr
74hc74/synthesis/d_ff.edn
74hc74/synthesis/d_ff.htm
74hc74/synthesis/d_ff.map
74hc74/synthesis/d_ff.pdc
74hc74/synthesis/d_ff.sdf
74hc74/synthesis/d_ff.so
74hc74/synthesis/d_ff.srd
74hc74/synthesis/d_ff.srm
74hc74/synthesis/d_ff.srr
74hc74/synthesis/d_ff.srs
74hc74/synthesis/d_ff.szr
74hc74/synthesis/d_ff.tlg
74hc74/synthesis/d_ff_sdc.sdc
74hc74/synthesis/d_ff_syn.prj
74hc74/synthesis/run_options.txt
74hc74/synthesis/stdout.log
74hc74/synthesis/syntmp/
74hc74/synthesis/syntmp/d_ff.plg
74hc74/synthesis/syntmp/d_ff_flink.htm
74hc74/synthesis/syntmp/d_ff_srr.htm
74hc74/synthesis/syntmp/d_ff_toc.htm
74hc74/viewdraw/
74hc74/viewdraw/sch/
74hc74/viewdraw/sym/
74hc74/viewdraw/vf/
74hc74/viewdraw/vf/project.lst
74hc74/viewdraw/viewdraw.ini
74hc74/viewdraw/wir/