要求在Quartus II软件，利用VHDL完成层次式电路设计，电路中的元件可以用VHDL设计也可以用库元件连线构成再封装。借助EDA工具中的综合器，适配器，时序仿真器和编程器等工具进行相应处理。输入方法不限制。适配采用Cyclone系列的EP1C6Q240C8。要求综合出RTL电路，并进行仿真输入波形设计并分析电路输出波形。要求采用层次式结构设计。-Quartus II software requires the use of VHDL complete hierarchical circuit design, circuit components can also be used with VHDL design library components constitute a re-package connection. With a comprehensive EDA tool, adapter, timing emulator and programming tools such as dealt with accordingly. Input method is not restricted. Adaptation by Cyclone series EP1C6Q240C8. Required to synthesize the RTL circuit, and simulated input waveform design and analysis of the circuit output waveform. Requires a hierarchical structure design.