standard/altera_avalon_sd_mmc_spi/
standard/altera_avalon_sd_mmc_spi/altera_avalon_sd_mmc_spi_sw.tcl
standard/altera_avalon_sd_mmc_spi/elca.gif
standard/altera_avalon_sd_mmc_spi/HAL/
standard/altera_avalon_sd_mmc_spi/HAL/inc/
standard/altera_avalon_sd_mmc_spi/HAL/inc/altera_avalon_sd_mmc_spi.h
standard/altera_avalon_sd_mmc_spi/HAL/lib/
standard/altera_avalon_sd_mmc_spi/HAL/lib/libaltera_avalon_sd_mmc_spi.a
standard/altera_avalon_sd_mmc_spi/HAL/lib/libaltera_avalon_sd_mmc_spi.a.debug
standard/altera_avalon_sd_mmc_spi/HAL/src/
standard/altera_avalon_sd_mmc_spi/HAL/src/component.mk
standard/altera_avalon_sd_mmc_spi/hdl/
standard/altera_avalon_sd_mmc_spi/hdl/ip_sd_mmc_spi.ocp
standard/altera_avalon_sd_mmc_spi/hdl/ip_sd_mmc_spi.vhd
standard/altera_avalon_sd_mmc_spi/inc/
standard/altera_avalon_sd_mmc_spi/inc/altera_avalon_sd_mmc_spi_regs.h
standard/altera_avalon_sd_mmc_spi/ip_sd_mmc_spi.ocp
standard/altera_avalon_sd_mmc_spi/ip_sd_mmc_spi.vhd
standard/altera_avalon_sd_mmc_spi/ip_sd_mmc_spi_hw.tcl
standard/altera_avalon_sd_mmc_spi/ip_sd_mmc_spi_wrapper.vhd
standard/altpllpll.ppf
standard/altpllpll.qip
standard/altpllpll.v
standard/altpllpll_bb.v
standard/alt_mem_phy_defines.v
standard/alt_mem_phy_sequencer.vhd
standard/auk_ddr_hp_controller.vhd
standard/auk_ddr_hp_init.ocp
standard/button_pio.v
standard/cpu.ocp
standard/cpu.sdc
standard/cpu.v
standard/cpu_bht_ram.mif
standard/cpu_dc_tag_ram.mif
standard/cpu_ddr_clock_bridge.v
standard/cpu_ic_tag_ram.mif
standard/cpu_jtag_debug_module_sysclk.v
standard/cpu_jtag_debug_module_tck.v
standard/cpu_jtag_debug_module_wrapper.v
standard/cpu_mult_cell.v
standard/cpu_ociram_default_contents.mif
standard/cpu_rf_ram_a.mif
standard/cpu_rf_ram_b.mif
standard/cpu_test_bench.v
standard/cycloneIII_3c25_niosII_standard.asm.rpt
standard/cycloneIII_3c25_niosII_standard.done
standard/cycloneIII_3c25_niosII_standard.fit.rpt
standard/cycloneIII_3c25_niosII_standard.fit.smsg
standard/cycloneIII_3c25_niosII_standard.fit.summary
standard/cycloneIII_3c25_niosII_standard.flow.rpt
standard/cycloneIII_3c25_niosII_standard.jdi
standard/cycloneIII_3c25_niosII_standard.map.rpt
standard/cycloneIII_3c25_niosII_standard.map.smsg
standard/cycloneIII_3c25_niosII_standard.map.summary
standard/cycloneIII_3c25_niosII_standard.pin
standard/cycloneIII_3c25_niosII_standard.qpf
standard/cycloneIII_3c25_niosII_standard.qsf
standard/cycloneIII_3c25_niosII_standard.qws
standard/cycloneIII_3c25_niosII_standard.sdc
standard/cycloneIII_3c25_niosII_standard.sof
standard/cycloneIII_3c25_niosII_standard.sta.rpt
standard/cycloneIII_3c25_niosII_standard.sta.summary
standard/cycloneIII_3c25_niosII_standard.v
standard/cycloneIII_3c25_niosII_standard_sopc.bsf
standard/cycloneIII_3c25_niosII_standard_sopc.ptf
standard/cycloneIII_3c25_niosII_standard_sopc.ptf.bak
standard/cycloneIII_3c25_niosII_standard_sopc.ptf.pre_generation_ptf
standard/cycloneIII_3c25_niosII_standard_sopc.qip
standard/cycloneIII_3c25_niosII_standard_sopc.sopc
standard/cycloneIII_3c25_niosII_standard_sopc.sopcinfo
standard/cycloneIII_3c25_niosII_standard_sopc.v
standard/cycloneIII_3c25_niosII_standard_sopc_clock_0.v
standard/cycloneIII_3c25_niosII_standard_sopc_clock_1.v
standard/cycloneIII_3c25_niosII_standard_sopc_generation_script
standard/cycloneIII_3c25_niosII_standard_sopc_log.txt
standard/ddr_o.v
standard/ddr_sdram.html
standard/ddr_sdram.ppf
standard/ddr_sdram.qip
standard/ddr_sdram.v
standard/ddr_sdram_advisor.ipa
standard/ddr_sdram_auk_ddr_hp_controller_wrapper.v
standard/ddr_sdram_controller_phy.v
standard/ddr_sdram_example_driver.v
standard/ddr_sdram_example_top.sdc
standard/ddr_sdram_example_top.v
standard/ddr_sdram_ex_lfsr8.v
standard/ddr_sdram_phy.html
standard/ddr_sdram_phy.qip
standard/ddr_sdram_phy.v
standard/ddr_sdram_phy_alt_mem_phy_ciii.v
standard/ddr_sdram_phy_alt_mem_phy_pll_ciii.ppf
standard/ddr_sdram_phy_alt_mem_phy_pll_ciii.qip
standard/ddr_sdram_phy_alt_mem_phy_pll_ciii.v
standard/ddr_sdram_phy_alt_mem_phy_pll_ciii.v_.bak
standard/ddr_sdram_phy_alt_mem_phy_pll_ciii_bb.v
standard/ddr_sdram_phy_alt_mem_phy_sequencer_wrapper.v
standard/ddr_sdram_phy_ddr_timing.sdc
standard/ddr_sdram_phy_simgen_init.txt
standard/ddr_sdram_phy_summary.csv
standard/flash_ssram_pipeline_bridge.v
standard/gmii_mii_mux.v
standard/high_res_timer.v
standard/jtag_uart.v
standard/led_pio.v
standard/performance_counter.v
standard/pipeline_bridge_before_tristate_bridge.v
standard/pll.sdc
standard/pll.v
standard/PLLJ_PLLSPE_INFO.txt
standard/readme.txt
standard/remote_update.v
standard/remote_update.vo
standard/slow_peripheral_bridge.v
standard/software_examples/
standard/software_examples/app/
standard/software_examples/app/board_diag/
standard/software_examples/app/board_diag/board_diag.c
standard/software_examples/app/board_diag/board_diag.h
standard/software_examples/app/board_diag/create-this-app
standard/software_examples/app/board_diag/readme.txt
standard/software_examples/app/count_binary/
standard/software_examples/app/count_binary/count_binary.c
standard/software_examples/app/count_binary/count_binary.h
standard/software_examples/app/count_binary/create-this-app
standar