文件名称:fenpin
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在modelsim环境下实现的计数器分频，希望和大家分享-Realized in the environment in modelsim frequency counter, would like to share
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test3/work/_info
test3/work/_temp/vlogkv43t2
test3/work/_temp/vlogixe61j
test3/work/_temp/vloga3ta10
test3/work/_temp/vlogz842c0
test3/work/_temp/vlogza46f0
test3/work/_temp/vlogztz6z1
test3/work/_vmake
test3/work/fdivision/_primary.vhd
test3/work/fdivision/_primary.dbs
test3/work/fdivision/_primary.dat
test3/work/fdivision/verilog.asm
test3/work/fdivision/verilog.rw
test3/work/division_@top/_primary.vhd
test3/work/division_@top/_primary.dbs
test3/work/division_@top/_primary.dat
test3/work/division_@top/verilog.asm
test3/work/division_@top/verilog.rw
test3/fdivision.v
test3/fdivision_Top.v
test3/fdivision.v.bak
test3/fdivision_Top.v.bak
test3/vsim.wlf
test3/fdivision.mpf
test3/fdivision.cr.mti
test3/work/_temp
test3/work/fdivision
test3/work/division_@top
test3/work
test3
test3/work/_temp/vlogkv43t2
test3/work/_temp/vlogixe61j
test3/work/_temp/vloga3ta10
test3/work/_temp/vlogz842c0
test3/work/_temp/vlogza46f0
test3/work/_temp/vlogztz6z1
test3/work/_vmake
test3/work/fdivision/_primary.vhd
test3/work/fdivision/_primary.dbs
test3/work/fdivision/_primary.dat
test3/work/fdivision/verilog.asm
test3/work/fdivision/verilog.rw
test3/work/division_@top/_primary.vhd
test3/work/division_@top/_primary.dbs
test3/work/division_@top/_primary.dat
test3/work/division_@top/verilog.asm
test3/work/division_@top/verilog.rw
test3/fdivision.v
test3/fdivision_Top.v
test3/fdivision.v.bak
test3/fdivision_Top.v.bak
test3/vsim.wlf
test3/fdivision.mpf
test3/fdivision.cr.mti
test3/work/_temp
test3/work/fdivision
test3/work/division_@top
test3/work
test3
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