文件名称:Verilog_HDL
介绍说明--下载内容来自于网络,使用问题请自行百度
在微型计算机系统中,CPU与外部的基本通信方式有两种,一种是并行通信即数据的各位同
时传送,其优点是传输速度较快,但数据有多少位就需要多少条传送线;而串行通信中数据一位一位顺序传
送,能节省传送线.用Vefilog HDL语言实现了串并、并串通信接口之间的转换-In the micro-computer systems, CPU basic communication with the outside there are two types of parallel data communication that you transmit at the same time, the advantage of faster transfer speeds, but the data how many how many transmission lines needed and the data in a serial communication send an order, to save transmission lines. With Vefilog HDL language to implement string and and the conversion between the serial communication interface
时传送,其优点是传输速度较快,但数据有多少位就需要多少条传送线;而串行通信中数据一位一位顺序传
送,能节省传送线.用Vefilog HDL语言实现了串并、并串通信接口之间的转换-In the micro-computer systems, CPU basic communication with the outside there are two types of parallel data communication that you transmit at the same time, the advantage of faster transfer speeds, but the data how many how many transmission lines needed and the data in a serial communication send an order, to save transmission lines. With Vefilog HDL language to implement string and and the conversion between the serial communication interface
(系统自动生成,下载前可以参看下载内容)
下载文件列表
用Verilog+HDL语言实现并串、串并接口的转换.pdf
1999-2046 搜珍网 All Rights Reserved.
本站作为网络服务提供者,仅为网络服务对象提供信息存储空间,仅对用户上载内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。
