文件名称:iiscode
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- 上传时间:2012-11-16
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文件大小:590.97kb
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用Verilog写的一个简单的IIs控制器,分为clkgen时钟分频模块和transcon传输控制模块。其中transcon模块主要部分为一个有限状态机实现的满足IIS标准的输出。
另附一个简单的Testcase以及得到的波形。-Develop an iis controller with verilog hdl. The key parts of iis were departed in two. One is clkgen.v which generate the clk and sync singnal we want and the transcon.v is used for contrl the FSM of the iis.
另附一个简单的Testcase以及得到的波形。-Develop an iis controller with verilog hdl. The key parts of iis were departed in two. One is clkgen.v which generate the clk and sync singnal we want and the transcon.v is used for contrl the FSM of the iis.
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下载文件列表
all code/clkgen.v
all code/clkgen.v~
all code/DUMP_FILE_iis.fsdb
all code/DUMP_FILE_iis.fsdb.fsdb
all code/novas.rc
all code/rt_shell_command.log
all code/runvcs
all code/runvcs~
all code/simv
all code/test.v
all code/test.v~
all code/top.v
all code/transcon.v
all code/transcon.v~
all code/vcs.key
all code/vcs.log
all code/vfastLog/pes.bat
all code/vfastLog/turbo.log
all code/simv.daidir/5NrI.tt
all code/simv.daidir/adhsoptmap.dat
all code/simv.daidir/AllModulesSkeletons.db
all code/simv.daidir/covg_defs
all code/simv.daidir/didmap.db
all code/simv.daidir/hsdefbe.db
all code/simv.daidir/hsim.db
all code/simv.daidir/hsim_bc.dat
all code/simv.daidir/hsim_elab.db
all code/simv.daidir/hsim_elabout.db
all code/simv.daidir/hsim_fegate.db
all code/simv.daidir/hsim_fs.dat
all code/simv.daidir/hsim_gate.db
all code/simv.daidir/hsim_gate_op_ip_map.dat
all code/simv.daidir/hsim_ldr.dat
all code/simv.daidir/hsim_lvl.db
all code/simv.daidir/hsim_merge.db
all code/simv.daidir/hsim_t0p.dat
all code/simv.daidir/hsim_tables.dat
all code/simv.daidir/iR5M_1.tt
all code/simv.daidir/mnmn.db
all code/simv.daidir/modfilename.db
all code/simv.daidir/offfilename.db
all code/simv.daidir/partition.db
all code/simv.daidir/rmapats.dat
all code/simv.daidir/str.db
all code/simv.daidir/topmodules
all code/simv.daidir/vcselabref.db
all code/simv.daidir/vcs_rebuild
all code/simv.daidir/_VCSgd_2l8Qsc_1.db
all code/simv.daidir/_VCSgd_2l8Qsc_1.did
all code/simv.daidir/_VCSgd_dnHAIe_1.db
all code/simv.daidir/_VCSgd_dnHAIe_1.did
all code/simv.daidir/_VCSgd_nGFE7b_1.db
all code/simv.daidir/_VCSgd_nGFE7b_1.did
all code/simv.daidir/_VCSgd_SrFmIc_1.db
all code/simv.daidir/_VCSgd_SrFmIc_1.did
all code/debussyLog/compiler.log
all code/debussyLog/debussy.cmd
all code/debussyLog/debussy.cmd.bak
all code/debussyLog/exe.log
all code/debussyLog/novas.rc
all code/debussyLog/pes.bat
all code/debussyLog/ToNetlist.log
all code/debussyLog/turbo.log
all code/debussyLog/verdi.log
all code/csrc/5NrIB_d.o
all code/csrc/5NrI_d.o
all code/csrc/5NrI_d.o.incr
all code/csrc/filelist
all code/csrc/idincr.db
all code/csrc/iR5M_1_d.o
all code/csrc/iR5M_1_d.o.incr
all code/csrc/Makefile
all code/csrc/product_timestamp
all code/csrc/rmapats.c
all code/csrc/rmapats.h
all code/csrc/rmapats.m
all code/csrc/rmapats.o
all code/csrc/rmapats_mop.o
all code/csrc/SIM_l.o
all code/csrc/vcsconst.incr
all code/csrc/vcspieces.incr
all code/csrc/vcstype.incr
all code/csrc/hsim/5NrI.dat
all code/csrc/hsim/5NrI_def.dat
all code/csrc/hsim/iR5M_1.dat
all code/csrc/hsim/iR5M_1_def.dat
all code/csrc/hsim
all code/vfastLog
all code/simv.daidir
all code/debussyLog
all code/csrc
all code
all code/clkgen.v~
all code/DUMP_FILE_iis.fsdb
all code/DUMP_FILE_iis.fsdb.fsdb
all code/novas.rc
all code/rt_shell_command.log
all code/runvcs
all code/runvcs~
all code/simv
all code/test.v
all code/test.v~
all code/top.v
all code/transcon.v
all code/transcon.v~
all code/vcs.key
all code/vcs.log
all code/vfastLog/pes.bat
all code/vfastLog/turbo.log
all code/simv.daidir/5NrI.tt
all code/simv.daidir/adhsoptmap.dat
all code/simv.daidir/AllModulesSkeletons.db
all code/simv.daidir/covg_defs
all code/simv.daidir/didmap.db
all code/simv.daidir/hsdefbe.db
all code/simv.daidir/hsim.db
all code/simv.daidir/hsim_bc.dat
all code/simv.daidir/hsim_elab.db
all code/simv.daidir/hsim_elabout.db
all code/simv.daidir/hsim_fegate.db
all code/simv.daidir/hsim_fs.dat
all code/simv.daidir/hsim_gate.db
all code/simv.daidir/hsim_gate_op_ip_map.dat
all code/simv.daidir/hsim_ldr.dat
all code/simv.daidir/hsim_lvl.db
all code/simv.daidir/hsim_merge.db
all code/simv.daidir/hsim_t0p.dat
all code/simv.daidir/hsim_tables.dat
all code/simv.daidir/iR5M_1.tt
all code/simv.daidir/mnmn.db
all code/simv.daidir/modfilename.db
all code/simv.daidir/offfilename.db
all code/simv.daidir/partition.db
all code/simv.daidir/rmapats.dat
all code/simv.daidir/str.db
all code/simv.daidir/topmodules
all code/simv.daidir/vcselabref.db
all code/simv.daidir/vcs_rebuild
all code/simv.daidir/_VCSgd_2l8Qsc_1.db
all code/simv.daidir/_VCSgd_2l8Qsc_1.did
all code/simv.daidir/_VCSgd_dnHAIe_1.db
all code/simv.daidir/_VCSgd_dnHAIe_1.did
all code/simv.daidir/_VCSgd_nGFE7b_1.db
all code/simv.daidir/_VCSgd_nGFE7b_1.did
all code/simv.daidir/_VCSgd_SrFmIc_1.db
all code/simv.daidir/_VCSgd_SrFmIc_1.did
all code/debussyLog/compiler.log
all code/debussyLog/debussy.cmd
all code/debussyLog/debussy.cmd.bak
all code/debussyLog/exe.log
all code/debussyLog/novas.rc
all code/debussyLog/pes.bat
all code/debussyLog/ToNetlist.log
all code/debussyLog/turbo.log
all code/debussyLog/verdi.log
all code/csrc/5NrIB_d.o
all code/csrc/5NrI_d.o
all code/csrc/5NrI_d.o.incr
all code/csrc/filelist
all code/csrc/idincr.db
all code/csrc/iR5M_1_d.o
all code/csrc/iR5M_1_d.o.incr
all code/csrc/Makefile
all code/csrc/product_timestamp
all code/csrc/rmapats.c
all code/csrc/rmapats.h
all code/csrc/rmapats.m
all code/csrc/rmapats.o
all code/csrc/rmapats_mop.o
all code/csrc/SIM_l.o
all code/csrc/vcsconst.incr
all code/csrc/vcspieces.incr
all code/csrc/vcstype.incr
all code/csrc/hsim/5NrI.dat
all code/csrc/hsim/5NrI_def.dat
all code/csrc/hsim/iR5M_1.dat
all code/csrc/hsim/iR5M_1_def.dat
all code/csrc/hsim
all code/vfastLog
all code/simv.daidir
all code/debussyLog
all code/csrc
all code
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