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文件名称:ver1.0
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- 上传时间：2012-11-16
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Shutdown of the UC1842 can be accomplished by two methods either raise pin 3 above 1 V or pull pin 1 below
a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high
(refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock
cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown
may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At
this pint the reference turns off, allowing the SCR to reset.-Shutdown of the UC1842 can be accomplished by two methods either raise pin 3 above 1 V or pull pin 1 below
a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high
(refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock
cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown
may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At
this pint the reference turns off, allowing the SCR to reset.
a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high
(refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock
cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown
may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At
this pint the reference turns off, allowing the SCR to reset.-Shutdown of the UC1842 can be accomplished by two methods either raise pin 3 above 1 V or pull pin 1 below
a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high
(refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock
cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown
may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At
this pint the reference turns off, allowing the SCR to reset.
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ver1.0.TXT
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