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文件名称:opencores

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.52mb
  • 已下载：
    0次
  • 提 供 者：
    den****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

opencores开源vhdl的部分代码,从原站cvs下来的最新代码-opencores part of the open source vhdl code, from the original station down the latest cvs code
(系统自动生成,下载前可以参看下载内容)

下载文件列表

minsoc/.svn/entries
minsoc/minsoc_latest[1].tar.gz
CORDIC/cordic/.svn/entries
CORDIC/cordic_latest[1].tar.gz
uart2bus/.svn/all-wcprops
uart2bus/.svn/entries
uart2bus/branches/.svn/all-wcprops
uart2bus/branches/.svn/entries
uart2bus/tags/.svn/all-wcprops
uart2bus/tags/.svn/entries
uart2bus/trunk/.svn/all-wcprops
uart2bus/trunk/.svn/entries
uart2bus/trunk/doc/.svn/all-wcprops
uart2bus/trunk/doc/.svn/entries
uart2bus/trunk/doc/.svn/prop-base/UART to Bus Core Specifications.pdf.svn-base
uart2bus/trunk/doc/.svn/text-base/UART to Bus Core Specifications.pdf.svn-base
uart2bus/trunk/doc/UART to Bus Core Specifications.pdf
uart2bus/trunk/scilab/.svn/all-wcprops
uart2bus/trunk/scilab/.svn/entries
uart2bus/trunk/scilab/.svn/text-base/calc_baud_gen.sce.svn-base
uart2bus/trunk/scilab/calc_baud_gen.sce
uart2bus/trunk/verilog/.svn/all-wcprops
uart2bus/trunk/verilog/.svn/entries
uart2bus/trunk/verilog/bench/.svn/all-wcprops
uart2bus/trunk/verilog/bench/.svn/entries
uart2bus/trunk/verilog/bench/.svn/text-base/reg_file_model.v.svn-base
uart2bus/trunk/verilog/bench/.svn/text-base/tb_bin_uart2bus_top.v.svn-base
uart2bus/trunk/verilog/bench/.svn/text-base/tb_txt_uart2bus_top.v.svn-base
uart2bus/trunk/verilog/bench/.svn/text-base/tb_uart2bus_top.v.svn-base
uart2bus/trunk/verilog/bench/.svn/text-base/timescale.v.svn-base
uart2bus/trunk/verilog/bench/.svn/text-base/uart_tasks.v.svn-base
uart2bus/trunk/verilog/bench/reg_file_model.v
uart2bus/trunk/verilog/bench/tb_bin_uart2bus_top.v
uart2bus/trunk/verilog/bench/tb_txt_uart2bus_top.v
uart2bus/trunk/verilog/bench/tb_uart2bus_top.v
uart2bus/trunk/verilog/bench/timescale.v
uart2bus/trunk/verilog/bench/uart_tasks.v
uart2bus/trunk/verilog/rtl/.svn/all-wcprops
uart2bus/trunk/verilog/rtl/.svn/entries
uart2bus/trunk/verilog/rtl/.svn/text-base/baud_gen.v.svn-base
uart2bus/trunk/verilog/rtl/.svn/text-base/uart2bus_top.v.svn-base
uart2bus/trunk/verilog/rtl/.svn/text-base/uart_parser.v.svn-base
uart2bus/trunk/verilog/rtl/.svn/text-base/uart_rx.v.svn-base
uart2bus/trunk/verilog/rtl/.svn/text-base/uart_top.v.svn-base
uart2bus/trunk/verilog/rtl/.svn/text-base/uart_tx.v.svn-base
uart2bus/trunk/verilog/rtl/baud_gen.v
uart2bus/trunk/verilog/rtl/uart2bus_top.v
uart2bus/trunk/verilog/rtl/uart_parser.v
uart2bus/trunk/verilog/rtl/uart_rx.v
uart2bus/trunk/verilog/rtl/uart_top.v
uart2bus/trunk/verilog/rtl/uart_tx.v
uart2bus/trunk/verilog/sim/.svn/all-wcprops
uart2bus/trunk/verilog/sim/.svn/entries
uart2bus/trunk/verilog/sim/icarus/.svn/all-wcprops
uart2bus/trunk/verilog/sim/icarus/.svn/entries
uart2bus/trunk/verilog/sim/icarus/.svn/prop-base/test.bin.svn-base
uart2bus/trunk/verilog/sim/icarus/.svn/text-base/block_bin.cfg.svn-base
uart2bus/trunk/verilog/sim/icarus/.svn/text-base/block_txt.cfg.svn-base
uart2bus/trunk/verilog/sim/icarus/.svn/text-base/compile_bin.bat.svn-base
uart2bus/trunk/verilog/sim/icarus/.svn/text-base/compile_txt.bat.svn-base
uart2bus/trunk/verilog/sim/icarus/.svn/text-base/gtk.bat.svn-base
uart2bus/trunk/verilog/sim/icarus/.svn/text-base/run.bat.svn-base
uart2bus/trunk/verilog/sim/icarus/.svn/text-base/test.bin.svn-base
uart2bus/trunk/verilog/sim/icarus/.svn/text-base/test.txt.svn-base
uart2bus/trunk/verilog/sim/icarus/block_bin.cfg
uart2bus/trunk/verilog/sim/icarus/block_txt.cfg
uart2bus/trunk/verilog/sim/icarus/compile_bin.bat
uart2bus/trunk/verilog/sim/icarus/compile_txt.bat
uart2bus/trunk/verilog/sim/icarus/gtk.bat
uart2bus/trunk/verilog/sim/icarus/run.bat
uart2bus/trunk/verilog/sim/icarus/test.bin
uart2bus/trunk/verilog/sim/icarus/test.txt
uart2bus/trunk/verilog/syn/.svn/all-wcprops
uart2bus/trunk/verilog/syn/.svn/entries
uart2bus/trunk/verilog/syn/altera/.svn/all-wcprops
uart2bus/trunk/verilog/syn/altera/.svn/entries
uart2bus/trunk/verilog/syn/altera/.svn/text-base/uart2bus.qpf.svn-base
uart2bus/trunk/verilog/syn/altera/.svn/text-base/uart2bus.qws.svn-base
uart2bus/trunk/verilog/syn/altera/.svn/text-base/uart2bus_top.qsf.svn-base
uart2bus/trunk/verilog/syn/altera/uart2bus.qpf
uart2bus/trunk/verilog/syn/altera/uart2bus.qws
uart2bus/trunk/verilog/syn/altera/uart2bus_top.qsf
uart2bus/trunk/verilog/syn/xilinx/.svn/all-wcprops
uart2bus/trunk/verilog/syn/xilinx/.svn/entries
uart2bus/trunk/verilog/syn/xilinx/.svn/text-base/uart2bus.xise.svn-base
uart2bus/trunk/verilog/syn/xilinx/uart2bus.xise
uart2bus/trunk/vhdl/.svn/all-wcprops
uart2bus/trunk/vhdl/.svn/entries
uart2bus/trunk/vhdl/.svn/prop-base/test.bin.svn-base
uart2bus/trunk/vhdl/.svn/text-base/test.bin.svn-base
uart2bus/trunk/vhdl/.svn/text-base/test.txt.svn-base
uart2bus/trunk/vhdl/bench/.svn/all-wcprops
uart2bus/trunk/vhdl/bench/.svn/entries
uart2bus/trunk/vhdl/bench/.svn/text-base/regFileModel.vhd.svn-base
uart2bus/trunk/vhdl/bench/.svn/text-base/uart2BusTop_bin_tb.vhd.svn-base
uart2bus/trunk/vhdl/bench/.svn/text-base/uart2BusTop_txt_tb.vhd.svn-base
uart2bus/trunk/vhdl/bench/regFileModel.vhd
uart2bus/trunk/vhdl/bench/uart2BusTop_bin_tb.vhd
uart2bus/trunk/vhdl/bench/uart2BusTop_txt_tb.vhd
uart2bus/trunk/vhdl/rtl/.svn/all-wcprops
uart2bus/trunk/vhdl/rtl/.svn/entries
uart2bus/trunk/vhdl/rtl/.svn/text-base/baudGen.vhd.svn-base
uart2bus/trunk/vhdl/rtl/

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