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文件名称:clock_VHDL

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  • 上传时间:
    2012-11-16
  • 文件大小:
    1017.12kb
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主要供学习FPGA的人员学习如何写VHDL程序之用,该程序实现了时钟的二分频等功能。-Primarily for learning FPGA-VHDL program to learn how to write use, the program achieved the second clock frequency and so on.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

clock_VHDL/__projnav.log
clock_VHDL/_impact.cmd
clock_VHDL/_impact.log
clock_VHDL/automake.log
clock_VHDL/bitgen.ut
clock_VHDL/clock._hrpt
clock_VHDL/clock.bgn
clock_VHDL/clock.bit
clock_VHDL/clock.bld
clock_VHDL/clock.cmd_log
clock_VHDL/clock.dhp
clock_VHDL/clock.drc
clock_VHDL/clock.gyd
clock_VHDL/clock.imp
clock_VHDL/clock.ise
clock_VHDL/clock.ise_ISE_Backup
clock_VHDL/clock.jed
clock_VHDL/clock.lfp
clock_VHDL/clock.lso
clock_VHDL/clock.mfd
clock_VHDL/clock.mrp
clock_VHDL/clock.nc1
clock_VHDL/clock.ncd
clock_VHDL/clock.ngc
clock_VHDL/clock.ngd
clock_VHDL/clock.ngm
clock_VHDL/clock.ngr
clock_VHDL/clock.pad
clock_VHDL/clock.pad_txt
clock_VHDL/clock.par
clock_VHDL/clock.pcf
clock_VHDL/clock.placed_ncd_tracker
clock_VHDL/clock.pnx
clock_VHDL/clock.prj
clock_VHDL/clock.routed_ncd_tracker
clock_VHDL/clock.rpt
clock_VHDL/clock.sch
clock_VHDL/clock.stx
clock_VHDL/clock.syr
clock_VHDL/clock.tim
clock_VHDL/clock.tspec
clock_VHDL/clock.twr
clock_VHDL/clock.twx
clock_VHDL/clock.ucf
clock_VHDL/clock.ucf.untf
clock_VHDL/clock.ut
clock_VHDL/clock.vhf
clock_VHDL/clock.vm6
clock_VHDL/clock.xml
clock_VHDL/clock.xpi
clock_VHDL/clock_build.xml
clock_VHDL/clock_last_par.ncd
clock_VHDL/clock_map.ncd
clock_VHDL/clock_map.ngm
clock_VHDL/clock_pad.csv
clock_VHDL/clock_pad.txt
clock_VHDL/clock_summary.html
clock_VHDL/decode47.spl
clock_VHDL/decode47.sym
clock_VHDL/decode47.vhd
clock_VHDL/fen1.spl
clock_VHDL/fen1.sym
clock_VHDL/fen1.vhd
clock_VHDL/fen100.spl
clock_VHDL/fen100.sym
clock_VHDL/fen100.vhd
clock_VHDL/fen24.spl
clock_VHDL/fen24.sym
clock_VHDL/fen24.vhd
clock_VHDL/fen60.spl
clock_VHDL/fen60.sym
clock_VHDL/fen60.vhd
clock_VHDL/pepExtractor.prj
clock_VHDL/sel.spl
clock_VHDL/sel.sym
clock_VHDL/sel.vhd
clock_VHDL/tmperr.err
clock_VHDL/xst/work/hdllib.ref
clock_VHDL/xst/work/hdpdeps.ref
clock_VHDL/xst/work/sub00/vhpl00.vho
clock_VHDL/xst/work/sub00/vhpl01.vho
clock_VHDL/xst/work/sub00/vhpl02.vho
clock_VHDL/xst/work/sub00/vhpl03.vho
clock_VHDL/xst/work/sub00/vhpl04.vho
clock_VHDL/xst/work/sub00/vhpl05.vho
clock_VHDL/xst/work/sub00/vhpl06.vho
clock_VHDL/xst/work/sub00/vhpl07.vho
clock_VHDL/xst/work/sub00/vhpl08.vho
clock_VHDL/xst/work/sub00/vhpl09.vho
clock_VHDL/xst/work/sub00/vhpl10.vho
clock_VHDL/xst/work/sub00/vhpl11.vho
clock_VHDL/xst/work/sub00/vhpl12.vho
clock_VHDL/xst/work/sub00/vhpl13.vho
clock_VHDL/clock_html/tim/cpldta_glossary.htm
clock_VHDL/clock_html/tim/cpldta_style.css
clock_VHDL/clock_html/tim/genreport.htm
clock_VHDL/clock_html/tim/leftnav.htm
clock_VHDL/clock_html/tim/report.htm
clock_VHDL/clock_html/tim/timing_report.htm
clock_VHDL/clock_html/tim/toc.css
clock_VHDL/clock_html/tim/topnav.htm
clock_VHDL/clock_html/images/acr2_logo.jpg
clock_VHDL/clock_html/images/blackBar.jpg
clock_VHDL/clock_html/images/cpldBanner.jpg
clock_VHDL/clock_html/images/cr2s_logo.jpg
clock_VHDL/clock_html/images/fitterRpt.jpg
clock_VHDL/clock_html/images/logo.jpg
clock_VHDL/clock_html/images/spacer.jpg
clock_VHDL/clock_html/images/timingRpt.jpg
clock_VHDL/clock_html/images/xa9500xl_logo.jpg
clock_VHDL/clock_html/images/xbr_logo.jpg
clock_VHDL/clock_html/images/xc9500_logo.jpg
clock_VHDL/clock_html/images/xc9500xl_logo.jpg
clock_VHDL/clock_html/images/xc9500xv_logo.jpg
clock_VHDL/clock_html/images/xpla3_logo.jpg
clock_VHDL/clock_html/fit/applet.htm
clock_VHDL/clock_html/fit/applet.js
clock_VHDL/clock_html/fit/appletref.htm
clock_VHDL/clock_html/fit/ascii.htm
clock_VHDL/clock_html/fit/ascii.tmp
clock_VHDL/clock_html/fit/asciidoc.htm
clock_VHDL/clock_html/fit/backtop.jpg
clock_VHDL/clock_html/fit/beginstraight.gif
clock_VHDL/clock_html/fit/blank.gif
clock_VHDL/clock_html/fit/blank.htm
clock_VHDL/clock_html/fit/briefview.jpg
clock_VHDL/clock_html/fit/check.htm
clock_VHDL/clock_html/fit/checkNS4.htm
clock_VHDL/clock_html/fit/contact.gif
clock_VHDL/clock_html/fit/coolrunnerII_logo.jpg
clock_VHDL/clock_html/fit/coolrunner_logo.jpg
clock_VHDL/clock_html/fit/defeqns.htm
clock_VHDL/clock_html/fit/education.gif
clock_VHDL/clock_html/fit/endmkt.gif
clock_VHDL/clock_html/fit/eqns.htm
clock_VHDL/clock_html/fit/eqns.js
clock_VHDL/clock_html/fit/equations.gif
clock_VHDL/clock_html/fit/equations.htm
clock_VHDL/clock_html/fit/equationsdoc.htm
clock_VHDL/clock_html/fit/errors.js
clock_VHDL/clock_html/fit/errors1.gif
clock_VHDL/clock_html/fit/errors2.gif
clock_VHDL/clock_html/fit/errorsdoc.htm
clock_VHDL/clock_html/fit/errs.htm
clock_VHDL/clock_html/fit/failtable.htm
clock_VHDL/clock_html/fit/failtable.js
clock_VHDL/clock_html/fit/failtabledoc.htm
clock_VHDL/clock_html/fit/fb.gif
clock_VHDL/clock_html/fit/fb1.gif
clock_VHDL/clock_html/fit/fbs.htm
clock_VHDL/clock_html/fit/fbs.js
clock_VHDL/clock_html/fit/fbs_FB1.htm
clock_VHDL/clock_html/fit/fbs_FB2.htm
clock_VHDL/clock_html/fit/fbs_FB3.htm
clock_VHDL/clock_html/fit/fbs_FB4.htm
clock_VHDL/clock_html/fit/fbs_FB5.htm
clock_VHDL/clock_html/fit/fbs_FB6.htm
clock_VHDL/clock_html/fit/fbs_FB7.htm
clock_VHDL/clock_html/fit/fbs_FB8.htm
clock_VHDL/clock_html/fit/fbs_FBdoc.htm
clock_VHDL/clock_html/fit/fbsdoc.htm
clock_VHDL/clock_html/fit/fbview.jpg
clock_VHDL/clock_html/fit/functionblock.gif
clock_VHDL/clock_html/fit/genmsg.htm
cl

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