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文件名称:Example-b8-2

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.97mb
  • 已下载：
    0次
  • 提 供 者：
    ca***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-Each project examples include the project files of the project, source files, report files and generate the results files, the reader can use Quartus II or the software to directly open the corresponding. Design source file type according to the design input into the source code or schematic diagram, etc.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Example-b8-2/Altera_lib_files/220model.txt
Example-b8-2/Altera_lib_files/220model.v
Example-b8-2/Altera_lib_files/220model.vhd
Example-b8-2/Altera_lib_files/220model_87.vhd
Example-b8-2/Altera_lib_files/220pack.vhd
Example-b8-2/Altera_lib_files/altera_mf.txt
Example-b8-2/Altera_lib_files/altera_mf.v
Example-b8-2/Altera_lib_files/altera_mf.vhd
Example-b8-2/Altera_lib_files/altera_mf_87.vhd
Example-b8-2/Altera_lib_files/altera_mf_components.vhd
Example-b8-2/Altera_lib_files/stratix_atoms.v
Example-b8-2/Altera_lib_files/stratix_atoms.vhd
Example-b8-2/Altera_lib_files/stratix_components.vhd
Example-b8-2/func_sim/dpram8x32.v
Example-b8-2/func_sim/func_sim.cr.mti
Example-b8-2/func_sim/func_sim.mpf
Example-b8-2/func_sim/func_sim_wave.wlf
Example-b8-2/func_sim/pllx2.v
Example-b8-2/func_sim/pll_ram.v
Example-b8-2/func_sim/pll_ram_tb.v
Example-b8-2/func_sim/transcript
Example-b8-2/func_sim/vsim.wlf
Example-b8-2/func_sim/wave.bmp
Example-b8-2/func_sim/wave.do
Example-b8-2/func_sim/work/dpram8x32/verilog.asm
Example-b8-2/func_sim/work/dpram8x32/_primary.dat
Example-b8-2/func_sim/work/dpram8x32/_primary.vhd
Example-b8-2/func_sim/work/pllx2/verilog.asm
Example-b8-2/func_sim/work/pllx2/_primary.dat
Example-b8-2/func_sim/work/pllx2/_primary.vhd
Example-b8-2/func_sim/work/pll_ram/verilog.asm
Example-b8-2/func_sim/work/pll_ram/_primary.dat
Example-b8-2/func_sim/work/pll_ram/_primary.vhd
Example-b8-2/func_sim/work/pll_ram_tb/verilog.asm
Example-b8-2/func_sim/work/pll_ram_tb/_primary.dat
Example-b8-2/func_sim/work/pll_ram_tb/_primary.vhd
Example-b8-2/func_sim/work/_info
Example-b8-2/pll_ram/cmp_state.ini
Example-b8-2/pll_ram/db/altsyncram_7bc1.tdf
Example-b8-2/pll_ram/db/pll_ram(0).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(0).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(1).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(1).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(2).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(2).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(3).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(3).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(4).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(4).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(5).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(5).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(6).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(6).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(7).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(7).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram.asm.qmsg
Example-b8-2/pll_ram/db/pll_ram.cmp.cdb
Example-b8-2/pll_ram/db/pll_ram.cmp.ddb
Example-b8-2/pll_ram/db/pll_ram.cmp.hdb
Example-b8-2/pll_ram/db/pll_ram.cmp.rdb
Example-b8-2/pll_ram/db/pll_ram.cmp.tdb
Example-b8-2/pll_ram/db/pll_ram.csf.qmsg
Example-b8-2/pll_ram/db/pll_ram.db_info
Example-b8-2/pll_ram/db/pll_ram.eda.qmsg
Example-b8-2/pll_ram/db/pll_ram.fit.qmsg
Example-b8-2/pll_ram/db/pll_ram.hif
Example-b8-2/pll_ram/db/pll_ram.icc
Example-b8-2/pll_ram/db/pll_ram.map.cdb
Example-b8-2/pll_ram/db/pll_ram.map.hdb
Example-b8-2/pll_ram/db/pll_ram.map.qmsg
Example-b8-2/pll_ram/db/pll_ram.pll_ram.sld_design_entry.sci
Example-b8-2/pll_ram/db/pll_ram.pre_map.hdb
Example-b8-2/pll_ram/db/pll_ram.project.hdb
Example-b8-2/pll_ram/db/pll_ram.rtlv.hdb
Example-b8-2/pll_ram/db/pll_ram.rtlv_sg.cdb
Example-b8-2/pll_ram/db/pll_ram.rtlv_sg_swap.cdb
Example-b8-2/pll_ram/db/pll_ram.sgdiff.cdb
Example-b8-2/pll_ram/db/pll_ram.sgdiff.hdb
Example-b8-2/pll_ram/db/pll_ram.signalprobe.cdb
Example-b8-2/pll_ram/db/pll_ram.tan.qmsg
Example-b8-2/pll_ram/db/pll_ram_cmp.qrpt
Example-b8-2/pll_ram/db/pll_ram_hier_info
Example-b8-2/pll_ram/db/pll_ram_syn_hier_info
Example-b8-2/pll_ram/dpram8x32.v
Example-b8-2/pll_ram/pllx2.v
Example-b8-2/pll_ram/pll_ram.asm.rpt
Example-b8-2/pll_ram/pll_ram.done
Example-b8-2/pll_ram/pll_ram.eda.rpt
Example-b8-2/pll_ram/pll_ram.fit.eqn
Example-b8-2/pll_ram/pll_ram.fit.rpt
Example-b8-2/pll_ram/pll_ram.flow.rpt
Example-b8-2/pll_ram/pll_ram.map.eqn
Example-b8-2/pll_ram/pll_ram.map.rpt
Example-b8-2/pll_ram/pll_ram.pin
Example-b8-2/pll_ram/pll_ram.pof
Example-b8-2/pll_ram/pll_ram.qpf
Example-b8-2/pll_ram/pll_ram.qsf
Example-b8-2/pll_ram/pll_ram.qws
Example-b8-2/pll_ram/pll_ram.sof
Example-b8-2/pll_ram/pll_ram.tan.rpt
Example-b8-2/pll_ram/pll_ram.tan.summary
Example-b8-2/pll_ram/pll_ram.v
Example-b8-2/pll_ram/simulation/modelsim/pll_ram.vo
Example-b8-2/pll_ram/simulation/modelsim/pll_ram_modelsim.xrf
Example-b8-2/pll_ram/simulation/modelsim/pll_ram_v.sdo
Example-b8-2/source/dpram8x32.v
Example-b8-2/source/dpram8x32_bb.v
Example-b8-2/source/dpram8x32_wave0.jpg
Example-b8-2/source/dpram8x32_wave1.jpg
Example-b8-2/source/dpram8x32_wave2.jpg
Example-b8-2/source/dpram8x32_wave3.jpg
Example-b8-2/source/dpram8x32_waveforms.html
Example-b8-2/source/pllx2.v
Example-b8-2/source/pllx2_bb.v
Example-b8-2/source/pll_ram.v
Example-b8-2/source/pll_ram_tb.v
Example-b8-2/source/post-simulation/modelsim/pll_ram.vo
Example-b8-2/source/post-simulation/modelsim/pll_ram_modelsim.xrf
Example-b8-2/source/post-simulation/modelsim/pll_ram_v.sdo
Example-b8-2/timing_sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
Example-b8-2/timing_sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
Example-b8-2/tim

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