此源代码是基于Verilog语言的“与-或-非”门电路 、用 case语句描述的 4 选 1 数据选择器、同步置数、同步清零的计数器 、用 always 过程语句描述的简单算术逻辑单元、用 begin-end 串行块产生信号波形 ，有广泛的应用，比如编码器领域。-This source code is based on the Verilog language, " and- or- not"　gate, with the case statement described in the 4 to 1 data selector, set the number of synchronization, the synchronization counter is cleared, the process of statement always described by simple arithmetic logic unit by serial block begin-end signal waveforms generated, there is a wide range of applications, such as encoder areas.