此源代码是基于Verilog语言的持续赋值方式定义的 2 选 1 多路选择器 、阻塞赋值方式定义的 2 选 1 多路选择器、非阻塞赋值、阻塞赋值、模为 60 的 BCD码加法计数器 、模为 60 的 BCD码加法计数器、BCD码—七段数码管显示译码器、用 casez 描述的数据选择器、隐含锁存器举例 ，特别是模为 60 的 BCD码加法计数器，这是我目前发现的最优源代码，应用于解码器领域。-This source code is based on the Verilog language define the continued assignment of 2-to-1 multiplexer, blocking assignments define the 2-to-1 multiplexer, non-blocking assignments, blocking assignments, module code for the addition of 60 BCD counters, BCD code module for the addition of 60 counters, BCD code- seven-segment LED display decoder, the data described by casez selector, for example hidden latch, in particular, the BCD model code for the addition of 60 counters, this is my found that the best current source code, the decoder used in the field.