介绍Verilog HDL, 内容包括：Verilog应用，Verilog语言的构成元素，结构级描述及仿真

，行为级描述及仿真，延时的特点及说明

介绍Verilog testbench，激励和控制和描述

结果的产生及验证，任务task及函数function

用户定义的基本单元(primitive)，可综合的Verilog描述风格等-Introduction Verilog HDL, including: Verilog applications, Verilog language of the elements, structure, level descr iption and simulation, behavioral-level descr iption and simulation, delay characteristics and note describes Verilog testbench, described the results of incentive and control and the generation and verification, the task task and function of the basic unit of user-defined function (primitive), can be integrated Verilog descr iption of style