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文件名称:Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Ex

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    2012-11-16
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介绍说明--下载内容来自于网络,使用问题请自行百度

来自于ALTERA官方网站。

本文档详细介绍怎样利用MAX® II CPLD 来实现脉冲宽度调制(PWM)。本设计还利用了MAX II CPLD 的内部用户闪存振荡器,不需要采用专门的外部时钟。

附有verilog源程序。-From ALTERA website. This document details how to use the MAX ® II CPLD to implement pulse width modulation (PWM). This design also uses the MAX II CPLD' s internal oscillator user flash memory, without using a special external clock. With verilog source.
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下载文件列表

利用MAX II CPLD 实现 脉冲宽度调制.pdf
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/code/pwm_main.v
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pulse_width_modulator.cr.mti
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pulse_width_modulator.mpf
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pwm_main.v
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pwm_sim.cr.mti
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/pwm_sim.mpf
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/test_pwm.v
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.bmp
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.do
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave2.bmp
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave2.do
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave3.bmp
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave3.do
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave4.bmp
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave4.do
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave5.bmp
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/wave5.do
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/altufm_osc0_altufm_osc_1p3/verilog.asm
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/altufm_osc0_altufm_osc_1p3/_primary.dat
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/altufm_osc0_altufm_osc_1p3/_primary.vhd
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen/verilog.asm
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen/_primary.dat
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen/_primary.vhd
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clk_gen/verilog.asm
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clk_gen/_primary.dat
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clk_gen/_primary.vhd
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/dutycycle/verilog.asm
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/dutycycle/_primary.dat
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/dutycycle/_primary.vhd
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/duty_cycle/verilog.asm
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/duty_cycle/_primary.dat
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/duty_cycle/_primary.vhd
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_gen/verilog.asm
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_gen/_primary.dat
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_gen/_primary.vhd
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_main/verilog.asm
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_main/_primary.dat
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pwm_main/_primary.vhd
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_pwm/verilog.asm
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_pwm/_primary.dat
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_pwm/_primary.vhd
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/modelsim/work/_info
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.db_info
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.eco.cdb
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/db/pwm_main.sld_design_entry.sci
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.asm.rpt
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.cdf
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.done
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.dpf
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.fit.rpt
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.fit.smsg
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.fit.summary
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.flow.rpt
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.map.rpt
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.map.summary
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Desig

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