verilogHDL source/source/王金明 verilog HDL实例.pdf
verilogHDL source/source/chap9/bidir.v
verilogHDL source/source/chap9/bidir2.v
verilogHDL source/source/chap9/code_83.v
verilogHDL source/source/chap9/decode47.v
verilogHDL source/source/chap9/decoder_38.v
verilogHDL source/source/chap9/dff.v
verilogHDL source/source/chap9/dff1.v
verilogHDL source/source/chap9/dff2.v
verilogHDL source/source/chap9/encoder8_3.v
verilogHDL source/source/chap9/gate1.v
verilogHDL source/source/chap9/gate2.v
verilogHDL source/source/chap9/gate3.v
verilogHDL source/source/chap9/jk_ff.v
verilogHDL source/source/chap9/johnson.v
verilogHDL source/source/chap9/latch_1.v
verilogHDL source/source/chap9/latch_2.v
verilogHDL source/source/chap9/latch_8.v
verilogHDL source/source/chap9/mac.v
verilogHDL source/source/chap9/mac_tp.v
verilogHDL source/source/chap9/map_lpm_ram.v
verilogHDL source/source/chap9/mpc.v
verilogHDL source/source/chap9/mpc_tp.v
verilogHDL source/source/chap9/mux_case.v
verilogHDL source/source/chap9/mux_if.v
verilogHDL source/source/chap9/parity.v
verilogHDL source/source/chap9/ram256x8.v
verilogHDL source/source/chap9/reg8.v
verilogHDL source/source/chap9/rom.v
verilogHDL source/source/chap9/serial_pal.v
verilogHDL source/source/chap9/shifter.v
verilogHDL source/source/chap9/tri_1.v
verilogHDL source/source/chap9/tri_2.v
verilogHDL source/source/chap9/updown_count.v
verilogHDL source/source/chap8/add8_tp.v
verilogHDL source/source/chap8/carry_udp.v
verilogHDL source/source/chap8/carry_udpx1.v
verilogHDL source/source/chap8/carry_udpx2.v
verilogHDL source/source/chap8/count8_tp.v
verilogHDL source/source/chap8/delay.v
verilogHDL source/source/chap8/dff.v
verilogHDL source/source/chap8/dff_udp.v
verilogHDL source/source/chap8/latch.v
verilogHDL source/source/chap8/mult_tp.v
verilogHDL source/source/chap8/mux31.v
verilogHDL source/source/chap8/mux_tp.v
verilogHDL source/source/chap8/random_tp.v
verilogHDL source/source/chap8/rom.v
verilogHDL source/source/chap8/test1.v
verilogHDL source/source/chap8/test2.v
verilogHDL source/source/chap8/time_dif.v
verilogHDL source/source/chap7/add4_1.v
verilogHDL source/source/chap7/add4_2.v
verilogHDL source/source/chap7/add4_3.v
verilogHDL source/source/chap7/count4.v
verilogHDL source/source/chap7/full_add1.v
verilogHDL source/source/chap7/full_add2.v
verilogHDL source/source/chap7/full_add3.v
verilogHDL source/source/chap7/full_add4.v
verilogHDL source/source/chap7/full_add5.v
verilogHDL source/source/chap7/half_add1.v
verilogHDL source/source/chap7/half_add2.v
verilogHDL source/source/chap7/half_add3.v
verilogHDL source/source/chap7/half_add4.v
verilogHDL source/source/chap7/mux2_1a.v
verilogHDL source/source/chap7/mux2_1b.v
verilogHDL source/source/chap7/mux2_1c.v
verilogHDL source/source/chap7/mux4_1a.v
verilogHDL source/source/chap7/mux4_1b.v
verilogHDL source/source/chap7/mux4_1c.v
verilogHDL source/source/chap7/mux4_1d.v
verilogHDL source/source/chap6/alutask.v
verilogHDL source/source/chap6/alu_tp.v
verilogHDL source/source/chap6/code_83.v
verilogHDL source/source/chap6/count.v
verilogHDL source/source/chap6/funct.v
verilogHDL source/source/chap6/funct_tp.v
verilogHDL source/source/chap6/paral1.v
verilogHDL source/source/chap6/paral2.v
verilogHDL source/source/chap6/serial1.v
verilogHDL source/source/chap6/serial2.v
verilogHDL source/source/chap5/adder.v
verilogHDL source/source/chap5/adder16.v
verilogHDL source/source/chap5/alu.v
verilogHDL source/source/chap5/block.v
verilogHDL source/source/chap5/buried_ff.v
verilogHDL source/source/chap5/compile.v
verilogHDL source/source/chap5/count.v
verilogHDL source/source/chap5/count60.v
verilogHDL source/source/chap5/decode4_7.v
verilogHDL source/source/chap5/loop1.v
verilogHDL source/source/chap5/loop2.v
verilogHDL source/source/chap5/loop3.v
verilogHDL source/source/chap5/mult_for.v
verilogHDL source/source/chap5/mult_repeat.v
verilogHDL source/source/chap5/mux21_1.v
verilogHDL source/source/chap5/mux21_2.v
verilogHDL source/source/chap5/mux4_1.v
verilogHDL source/source/chap5/mux_casez.v
verilogHDL source/source/chap5/non_block.v
verilogHDL source/source/chap5/test.v
verilogHDL source/source/chap5/voter7.v
verilogHDL source/source/chap5/wave1.v
verilogHDL source/source/chap5/wave2.v
verilogHDL source/source/chap3/adder4.v
verilogHDL source/source/chap3/adder_tp.v
verilogHDL source/source/chap3/aoi.v
verilogHDL source/source/chap3/count4.v
verilogHDL source/source/chap3/count4_tp.v
verilogHDL source/source/chap3/adder4.acf
verilogHDL source/source/chap3/adder4.ndb
verilogHDL source/source/chap3/adder4.hif
verilogHDL source/source/chap12/add_ahead.v
verilogHDL source/source/chap12/add_bx.v
verilogHDL source/source/chap12/add_jl.v
verilogHDL source/source/chap12/add_tree.v
verilogHDL source/source/chap12/correlator.v
verilogHDL source/source/chap12/crc.v
verilogHDL source/source/chap12/cycle.v
verilogHDL source/source/chap12/decoder1.v
verilogHDL source/source/chap12/decoder2.v
verilogHDL source/source/chap12/fir.v
verilogHDL source/source/chap12/linear.v
verilogHDL source/source/chap12/mult.v
verilogHDL source/source/chap12/mult4x4.v
verilogHDL sour