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文件名称:Group27_lab5

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
  • 上传时间：
    2012-11-16
  • 文件大小：
    417.03kb
  • 已下载：
    0次
  • 提 供 者：
    都***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

VHDL的基本门，ram，rom等的实现-VHDL basic door, ram, rom, etc. to achieve
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Group27_lab5/
Group27_lab5/Group27_lab5/
Group27_lab5/Group27_lab5/lab4(screen_shoot)/
Group27_lab5/Group27_lab5/lab4(screen_shoot)/comparator.jpg
Group27_lab5/Group27_lab5/lab4(screen_shoot)/four_bit_syn_counter.jpg
Group27_lab5/Group27_lab5/lab4(screen_shoot)/four_bit_syn_up_down_counter.jpg
Group27_lab5/Group27_lab5/lab4(screen_shoot)/incrementer.jpg
Group27_lab5/Group27_lab5/lab4(screen_shoot)/modulo_counter_with_asyn_reset.jpg
Group27_lab5/Group27_lab5/lab4(screen_shoot)/modulo_counter_with_enable.jpg
Group27_lab5/Group27_lab5/lab4(screen_shoot)/modulo_counter_with_syn_reset.jpg
Group27_lab5/Group27_lab5/lab4(screen_shoot)/nbit_counter_with_load.jpg
Group27_lab5/Group27_lab5/lab4(screen_shoot)/Thumbs.db
Group27_lab5/Group27_lab5/lab4(screen_shoot)/washer_controller.jpg
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/automake.log
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/d_flipflop.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/d_flipflop_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/eight_bit_comparator.ucf
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/eight_bit_comparator.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/eight_bit_compartor_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/eight_bit_modulo_counter_asyn_reset.ucf
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/eight_bit_modulo_counter_syn_reset.ucf
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/eight_bit_modulo_counter_syn_reset.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/eight_input_nor.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/enable_logic.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/enable_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/four_bit_adder_subtractor.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/four_bit_adder_subtractor_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/four_bit_LAC.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/four_bit_LAC_adder.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/four_bit_reg.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/four_bit_synchronous_counter.ucf
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/four_bit_synchronous_counter.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/four_bit_synchronous_counter_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/four_bit_synchronous_up_down_counter.ucf
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/four_bit_synchronous_up_down_counter.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/four_bit_synchronous_up_down_counter_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/four_bit_syn_up_down_counter_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/full_adder.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/half_adder.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/lab4.dhp
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/lab4.ise
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/lab4.ise_ISE_Backup
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/modulo_counter_asyn_reset.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/modulo_counter_syn_reset_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/modulo_counter_with_asyn_reset_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_count_enable.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_count_enable_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_incrementer.ucf
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_incrementer.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_incrementer_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_reg.ucf
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_reg.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_reg_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_reg_timesim.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_ripple_counter.ucf
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_ripple_counter.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_ripple_counter_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_synchronous_counter_with_parallel_load_input.ucf
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_synchronous_counter_with_parallel_load_input.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_synchronous_counter_with_parallel_load_input_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_syn_counter_enable.ucf
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_syn_counter_enable.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_syn_counter_enable_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_syn_counter_with_load.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/nbit_xor_contol.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/next_state_logic.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/n_bit_adder.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/n_bit_two_input_mux.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/two_input_mux.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/two_input_or.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/two_input_xor.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/T_flipflop.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/washer_controller.ucf
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/washer_controller.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/washer_controller_tb.vhd
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/washer_next_state_logic.ucf
Group27_lab5/Group27_lab5/lab4(vhdl+ucf)/washer_next_state_logic.vhd
Group27_lab5/Grou

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