文件名称:stratixIII_3sl150_dev_TSE_SGMII_v1
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- 上传时间：2012-11-16
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文件大小：6.91mb
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该程序实现altera开发板 stratix III 3S150通过以太网与pc之间通信。 使用Quartus II和Nios II 设计。
因为altera官方没有这块板子的正确网卡与pc通信的程序，-Overall
This example works at 1000M/100M/10M Base SGMII mode on SIII 3S150 Kit.
Designed by Quartus II/IP Cores/Nios II EDS v8.0
This is not an official released Design Example. It is only for your reference, but beyond the support area of ALTERA Mysupport.
因为altera官方没有这块板子的正确网卡与pc通信的程序，-Overall
This example works at 1000M/100M/10M Base SGMII mode on SIII 3S150 Kit.
Designed by Quartus II/IP Cores/Nios II EDS v8.0
This is not an official released Design Example. It is only for your reference, but beyond the support area of ALTERA Mysupport.
相关搜索： NIOS II EDS
stratix 3
(系统自动生成,下载前可以参看下载内容)
下载文件列表
stratixIII_3sl150_dev_TSE_SGMII_v1/.sopc_builder/
stratixIII_3sl150_dev_TSE_SGMII_v1/.sopc_builder/install.ptf
stratixIII_3sl150_dev_TSE_SGMII_v1/.sopc_builder/install2.ptf
stratixIII_3sl150_dev_TSE_SGMII_v1/.sopc_builder/preferences.xml
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr.html
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr.ppf
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr.qip
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_advisor.ipa
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_auk_ddr_hp_controller_wrapper.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_bridge.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_controller_phy.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_driver.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top.sdc
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top.v.tmp
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top.v.tmp2
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top_2.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top_3.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top_4.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top_5.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top_6.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top_7.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_ex_lfsr8.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy.html
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy.qip
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii.bsf
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii.ppf
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii.qip
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii.v_.bak
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii_bb.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii_inst.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_sequencer_wrapper.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_siii.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_assign_dq_groups.tcl
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_autodetectedpins.tcl
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_ddr_pins.tcl
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_ddr_timing.sdc
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_report_timing.tcl
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_simgen_init.txt
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_summary.csv
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_pin_assignments.tcl
stratixIII_3sl150_dev_TSE_SGMII_v1/altpllsys_pll.bsf
stratixIII_3sl150_dev_TSE_SGMII_v1/altpllsys_pll.ppf
stratixIII_3sl150_dev_TSE_SGMII_v1/altpllsys_pll.qip
stratixIII_3sl150_dev_TSE_SGMII_v1/altpllsys_pll.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altpllsys_pll_bb.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altpllsys_pll_inst.v
stratixIII_3sl150_dev_TSE_SGMII_v1/alt_mem_phy_defines.v
stratixIII_3sl150_dev_TSE_SGMII_v1/alt_mem_phy_sequencer.vhd
stratixIII_3sl150_dev_TSE_SGMII_v1/auk_ddr2_hp_init.ocp
stratixIII_3sl150_dev_TSE_SGMII_v1/auk_ddr_hp_controller.vhd
stratixIII_3sl150_dev_TSE_SGMII_v1/button_pio.v
stratixIII_3sl150_dev_TSE_SGMII_v1/clock_0.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu.ocp
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu.sdc
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_bht_ram.mif
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_dc_tag_ram.mif
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_ic_tag_ram.mif
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_interrupt_vector.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_jtag_debug_module.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_jtag_debug_module_sysclk.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_jtag_debug_module_tck.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_jtag_debug_module_wrapper.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_mult_cell.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_ociram_default_contents.mif
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_rf_ram_a.mif
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_rf_ram_b.mif
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_test_bench.v
stratixIII_3sl150_dev_TSE_SGMII_v1/ddr_o.bsf
stratixIII_3sl150_dev_TSE_SGMII_v1/ddr_o.ppf
stratixIII_3sl150_dev_TSE_SGMII_v1/ddr_o.qip
stratixIII_3sl150_dev_TSE_SGMII_v1/ddr_o.v
stratixIII_3sl150_dev_TSE_SGMII_v1/ddr_o_bb.v
stratixIII_3sl150_dev_TSE_SGMII_v1/ddr_o_inst.v
stratixIII_3sl150_dev_TSE_SGMII_v1/descriptor_memory.hex
stratixIII_3sl150_dev_TSE_SGMII_v1/descriptor_memory.v
stratixIII_3sl150_dev_TSE_SGMII_v1/documents/
stratixIII_3sl150_dev_TSE_SGMII_v1/documents/SIII_3S150_Kit_1000_100_10M_Base_SGMII_v1.doc
stratixIII_3sl150_dev_TSE_SGMII_v1/gmii_mii_mux.v
stratixIII_3sl150_dev_TSE_SGMII_v1/hight_res_timer.v
stratixIII_3sl150_dev_TSE_SGMII_v1/jtag_uart.v
stratixIII_3sl150_dev_TSE_SGMII_v1/lcd.v
stratixIII_3sl150_dev_TSE_SGMII_v1/led_pio.v
stratixIII_3sl150_dev_TSE_SGMII_v1/onchip_ram.hex
stratixIII_3sl150_dev_TS
stratixIII_3sl150_dev_TSE_SGMII_v1/.sopc_builder/install.ptf
stratixIII_3sl150_dev_TSE_SGMII_v1/.sopc_builder/install2.ptf
stratixIII_3sl150_dev_TSE_SGMII_v1/.sopc_builder/preferences.xml
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr.html
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr.ppf
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr.qip
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_advisor.ipa
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_auk_ddr_hp_controller_wrapper.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_bridge.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_controller_phy.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_driver.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top.sdc
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top.v.tmp
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top.v.tmp2
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top_2.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top_3.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top_4.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top_5.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top_6.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_example_top_7.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_ex_lfsr8.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy.html
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy.qip
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii.bsf
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii.ppf
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii.qip
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii.v_.bak
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii_bb.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_pll_siii_inst.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_sequencer_wrapper.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_alt_mem_phy_siii.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_assign_dq_groups.tcl
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_autodetectedpins.tcl
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_ddr_pins.tcl
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_ddr_timing.sdc
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_report_timing.tcl
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_simgen_init.txt
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_phy_summary.csv
stratixIII_3sl150_dev_TSE_SGMII_v1/altmemddr_pin_assignments.tcl
stratixIII_3sl150_dev_TSE_SGMII_v1/altpllsys_pll.bsf
stratixIII_3sl150_dev_TSE_SGMII_v1/altpllsys_pll.ppf
stratixIII_3sl150_dev_TSE_SGMII_v1/altpllsys_pll.qip
stratixIII_3sl150_dev_TSE_SGMII_v1/altpllsys_pll.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altpllsys_pll_bb.v
stratixIII_3sl150_dev_TSE_SGMII_v1/altpllsys_pll_inst.v
stratixIII_3sl150_dev_TSE_SGMII_v1/alt_mem_phy_defines.v
stratixIII_3sl150_dev_TSE_SGMII_v1/alt_mem_phy_sequencer.vhd
stratixIII_3sl150_dev_TSE_SGMII_v1/auk_ddr2_hp_init.ocp
stratixIII_3sl150_dev_TSE_SGMII_v1/auk_ddr_hp_controller.vhd
stratixIII_3sl150_dev_TSE_SGMII_v1/button_pio.v
stratixIII_3sl150_dev_TSE_SGMII_v1/clock_0.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu.ocp
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu.sdc
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_bht_ram.mif
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_dc_tag_ram.mif
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_ic_tag_ram.mif
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_interrupt_vector.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_jtag_debug_module.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_jtag_debug_module_sysclk.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_jtag_debug_module_tck.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_jtag_debug_module_wrapper.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_mult_cell.v
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_ociram_default_contents.mif
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_rf_ram_a.mif
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_rf_ram_b.mif
stratixIII_3sl150_dev_TSE_SGMII_v1/cpu_test_bench.v
stratixIII_3sl150_dev_TSE_SGMII_v1/ddr_o.bsf
stratixIII_3sl150_dev_TSE_SGMII_v1/ddr_o.ppf
stratixIII_3sl150_dev_TSE_SGMII_v1/ddr_o.qip
stratixIII_3sl150_dev_TSE_SGMII_v1/ddr_o.v
stratixIII_3sl150_dev_TSE_SGMII_v1/ddr_o_bb.v
stratixIII_3sl150_dev_TSE_SGMII_v1/ddr_o_inst.v
stratixIII_3sl150_dev_TSE_SGMII_v1/descriptor_memory.hex
stratixIII_3sl150_dev_TSE_SGMII_v1/descriptor_memory.v
stratixIII_3sl150_dev_TSE_SGMII_v1/documents/
stratixIII_3sl150_dev_TSE_SGMII_v1/documents/SIII_3S150_Kit_1000_100_10M_Base_SGMII_v1.doc
stratixIII_3sl150_dev_TSE_SGMII_v1/gmii_mii_mux.v
stratixIII_3sl150_dev_TSE_SGMII_v1/hight_res_timer.v
stratixIII_3sl150_dev_TSE_SGMII_v1/jtag_uart.v
stratixIII_3sl150_dev_TSE_SGMII_v1/lcd.v
stratixIII_3sl150_dev_TSE_SGMII_v1/led_pio.v
stratixIII_3sl150_dev_TSE_SGMII_v1/onchip_ram.hex
stratixIII_3sl150_dev_TS
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