文件名称:S5_UART
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- 上传时间:2012-11-16
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文件大小:1.06mb
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已下载:0次
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相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
红色飓风的uart程序,我买的开发板的网站的历程-Red Hurricane uart procedure, I bought the course of the development board' s website
(系统自动生成,下载前可以参看下载内容)
下载文件列表
S5_UART/Doc/sscom.ini
S5_UART/Doc/sscom32.exe
S5_UART/Doc/UART控制器设计说明.doc
S5_UART/Doc/xapp341.pdf
S5_UART/func_sim/rcvr.v
S5_UART/func_sim/transcript
S5_UART/func_sim/txmit.v
S5_UART/func_sim/txmit_tf.do
S5_UART/func_sim/uart.cr.mti
S5_UART/func_sim/uart.mpf
S5_UART/func_sim/uart.v
S5_UART/func_sim/uart_if.v
S5_UART/func_sim/uart_tb.do
S5_UART/func_sim/uart_tb.v
S5_UART/func_sim/uart_tb_fixed.do
S5_UART/func_sim/vish_stacktrace.vstf
S5_UART/func_sim/vsim.wlf
S5_UART/func_sim/wave.do
S5_UART/func_sim/work/@u@a@r@t_tb/verilog.asm
S5_UART/func_sim/work/@u@a@r@t_tb/_primary.dat
S5_UART/func_sim/work/@u@a@r@t_tb/_primary.vhd
S5_UART/func_sim/work/rcvr/verilog.asm
S5_UART/func_sim/work/rcvr/_primary.dat
S5_UART/func_sim/work/rcvr/_primary.vhd
S5_UART/func_sim/work/txmit/verilog.asm
S5_UART/func_sim/work/txmit/_primary.dat
S5_UART/func_sim/work/txmit/_primary.vhd
S5_UART/func_sim/work/uart/verilog.asm
S5_UART/func_sim/work/uart/_primary.dat
S5_UART/func_sim/work/uart/_primary.vhd
S5_UART/func_sim/work/uart_if/verilog.asm
S5_UART/func_sim/work/uart_if/_primary.dat
S5_UART/func_sim/work/uart_if/_primary.vhd
S5_UART/func_sim/work/_info
S5_UART/physical/altclklock0.bsf
S5_UART/physical/altclklock0.v
S5_UART/physical/altclklock0_bb.v
S5_UART/physical/async_transmitter.bsf
S5_UART/physical/cmp_state.ini
S5_UART/physical/div.bsf
S5_UART/physical/div_2.bsf
S5_UART/physical/div_2.v
S5_UART/physical/filter.bsf
S5_UART/physical/LED_flush.bsf
S5_UART/physical/rcvr.bsf
S5_UART/physical/simulation/modelsim/cyclone_atoms.v
S5_UART/physical/simulation/modelsim/uart_if.vo
S5_UART/physical/simulation/modelsim/uart_if_modelsim.xrf
S5_UART/physical/simulation/modelsim/uart_if_v.sdo
S5_UART/physical/simulation/modelsim/uart_post.cr.mti
S5_UART/physical/simulation/modelsim/uart_post.mpf
S5_UART/physical/simulation/modelsim/work/@p@r@i@m_@d@f@f@e/verilog.asm
S5_UART/physical/simulation/modelsim/work/@p@r@i@m_@d@f@f@e/_primary.dat
S5_UART/physical/simulation/modelsim/work/@p@r@i@m_@d@f@f@e/_primary.vhd
S5_UART/physical/simulation/modelsim/work/@u@a@r@t_tb/verilog.asm
S5_UART/physical/simulation/modelsim/work/@u@a@r@t_tb/_primary.dat
S5_UART/physical/simulation/modelsim/work/@u@a@r@t_tb/_primary.vhd
S5_UART/physical/simulation/modelsim/work/and1/verilog.asm
S5_UART/physical/simulation/modelsim/work/and1/_primary.dat
S5_UART/physical/simulation/modelsim/work/and1/_primary.vhd
S5_UART/physical/simulation/modelsim/work/and16/verilog.asm
S5_UART/physical/simulation/modelsim/work/and16/_primary.dat
S5_UART/physical/simulation/modelsim/work/and16/_primary.vhd
S5_UART/physical/simulation/modelsim/work/b17mux21/verilog.asm
S5_UART/physical/simulation/modelsim/work/b17mux21/_primary.dat
S5_UART/physical/simulation/modelsim/work/b17mux21/_primary.vhd
S5_UART/physical/simulation/modelsim/work/b5mux21/verilog.asm
S5_UART/physical/simulation/modelsim/work/b5mux21/_primary.dat
S5_UART/physical/simulation/modelsim/work/b5mux21/_primary.vhd
S5_UART/physical/simulation/modelsim/work/bmux21/verilog.asm
S5_UART/physical/simulation/modelsim/work/bmux21/_primary.dat
S5_UART/physical/simulation/modelsim/work/bmux21/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_asmiblock/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_asmiblock/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_asmiblock/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_asynch_io/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_asynch_io/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_asynch_io/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_asynch_lcell/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_asynch_lcell/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_asynch_lcell/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_crcblock/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_crcblock/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_crcblock/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_dll/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_dll/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_dll/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_io/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_io/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_io/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_jtag/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_jtag/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_jtag/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_lcell/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_lcell/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_lcell/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_lcell_register/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_lcell_register/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_lcell_register/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_pll/verilog.asm
S5_UA
S5_UART/Doc/sscom32.exe
S5_UART/Doc/UART控制器设计说明.doc
S5_UART/Doc/xapp341.pdf
S5_UART/func_sim/rcvr.v
S5_UART/func_sim/transcript
S5_UART/func_sim/txmit.v
S5_UART/func_sim/txmit_tf.do
S5_UART/func_sim/uart.cr.mti
S5_UART/func_sim/uart.mpf
S5_UART/func_sim/uart.v
S5_UART/func_sim/uart_if.v
S5_UART/func_sim/uart_tb.do
S5_UART/func_sim/uart_tb.v
S5_UART/func_sim/uart_tb_fixed.do
S5_UART/func_sim/vish_stacktrace.vstf
S5_UART/func_sim/vsim.wlf
S5_UART/func_sim/wave.do
S5_UART/func_sim/work/@u@a@r@t_tb/verilog.asm
S5_UART/func_sim/work/@u@a@r@t_tb/_primary.dat
S5_UART/func_sim/work/@u@a@r@t_tb/_primary.vhd
S5_UART/func_sim/work/rcvr/verilog.asm
S5_UART/func_sim/work/rcvr/_primary.dat
S5_UART/func_sim/work/rcvr/_primary.vhd
S5_UART/func_sim/work/txmit/verilog.asm
S5_UART/func_sim/work/txmit/_primary.dat
S5_UART/func_sim/work/txmit/_primary.vhd
S5_UART/func_sim/work/uart/verilog.asm
S5_UART/func_sim/work/uart/_primary.dat
S5_UART/func_sim/work/uart/_primary.vhd
S5_UART/func_sim/work/uart_if/verilog.asm
S5_UART/func_sim/work/uart_if/_primary.dat
S5_UART/func_sim/work/uart_if/_primary.vhd
S5_UART/func_sim/work/_info
S5_UART/physical/altclklock0.bsf
S5_UART/physical/altclklock0.v
S5_UART/physical/altclklock0_bb.v
S5_UART/physical/async_transmitter.bsf
S5_UART/physical/cmp_state.ini
S5_UART/physical/div.bsf
S5_UART/physical/div_2.bsf
S5_UART/physical/div_2.v
S5_UART/physical/filter.bsf
S5_UART/physical/LED_flush.bsf
S5_UART/physical/rcvr.bsf
S5_UART/physical/simulation/modelsim/cyclone_atoms.v
S5_UART/physical/simulation/modelsim/uart_if.vo
S5_UART/physical/simulation/modelsim/uart_if_modelsim.xrf
S5_UART/physical/simulation/modelsim/uart_if_v.sdo
S5_UART/physical/simulation/modelsim/uart_post.cr.mti
S5_UART/physical/simulation/modelsim/uart_post.mpf
S5_UART/physical/simulation/modelsim/work/@p@r@i@m_@d@f@f@e/verilog.asm
S5_UART/physical/simulation/modelsim/work/@p@r@i@m_@d@f@f@e/_primary.dat
S5_UART/physical/simulation/modelsim/work/@p@r@i@m_@d@f@f@e/_primary.vhd
S5_UART/physical/simulation/modelsim/work/@u@a@r@t_tb/verilog.asm
S5_UART/physical/simulation/modelsim/work/@u@a@r@t_tb/_primary.dat
S5_UART/physical/simulation/modelsim/work/@u@a@r@t_tb/_primary.vhd
S5_UART/physical/simulation/modelsim/work/and1/verilog.asm
S5_UART/physical/simulation/modelsim/work/and1/_primary.dat
S5_UART/physical/simulation/modelsim/work/and1/_primary.vhd
S5_UART/physical/simulation/modelsim/work/and16/verilog.asm
S5_UART/physical/simulation/modelsim/work/and16/_primary.dat
S5_UART/physical/simulation/modelsim/work/and16/_primary.vhd
S5_UART/physical/simulation/modelsim/work/b17mux21/verilog.asm
S5_UART/physical/simulation/modelsim/work/b17mux21/_primary.dat
S5_UART/physical/simulation/modelsim/work/b17mux21/_primary.vhd
S5_UART/physical/simulation/modelsim/work/b5mux21/verilog.asm
S5_UART/physical/simulation/modelsim/work/b5mux21/_primary.dat
S5_UART/physical/simulation/modelsim/work/b5mux21/_primary.vhd
S5_UART/physical/simulation/modelsim/work/bmux21/verilog.asm
S5_UART/physical/simulation/modelsim/work/bmux21/_primary.dat
S5_UART/physical/simulation/modelsim/work/bmux21/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_asmiblock/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_asmiblock/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_asmiblock/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_asynch_io/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_asynch_io/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_asynch_io/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_asynch_lcell/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_asynch_lcell/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_asynch_lcell/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_crcblock/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_crcblock/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_crcblock/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_dll/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_dll/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_dll/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_io/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_io/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_io/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_jtag/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_jtag/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_jtag/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_lcell/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_lcell/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_lcell/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_lcell_register/verilog.asm
S5_UART/physical/simulation/modelsim/work/cyclone_lcell_register/_primary.dat
S5_UART/physical/simulation/modelsim/work/cyclone_lcell_register/_primary.vhd
S5_UART/physical/simulation/modelsim/work/cyclone_pll/verilog.asm
S5_UA
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