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文件名称:S6_VGA_change

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    700.39kb
  • 已下载：
    0次
  • 提 供 者：
    blu****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

红色飓风的VGA程序，我买的开发板的网站的历程-Red Hurricane VGA procedure, I bought the course of the development board' s website
(系统自动生成,下载前可以参看下载内容)

下载文件列表

S6_VGA_change/Doc/程序说明.txt
S6_VGA_change/Proj/cmp_state.ini
S6_VGA_change/Proj/ColorBar.asm.rpt
S6_VGA_change/Proj/ColorBar.cdf
S6_VGA_change/Proj/ColorBar.done
S6_VGA_change/Proj/ColorBar.eda.rpt
S6_VGA_change/Proj/ColorBar.fit.eqn
S6_VGA_change/Proj/ColorBar.fit.rpt
S6_VGA_change/Proj/ColorBar.fit.smsg
S6_VGA_change/Proj/ColorBar.fit.summary
S6_VGA_change/Proj/ColorBar.flow.rpt
S6_VGA_change/Proj/ColorBar.jdi
S6_VGA_change/Proj/ColorBar.map.eqn
S6_VGA_change/Proj/ColorBar.map.rpt
S6_VGA_change/Proj/ColorBar.map.summary
S6_VGA_change/Proj/ColorBar.mif
S6_VGA_change/Proj/ColorBar.pin
S6_VGA_change/Proj/ColorBar.pof
S6_VGA_change/Proj/ColorBar.qpf
S6_VGA_change/Proj/ColorBar.qsf
S6_VGA_change/Proj/ColorBar.sof
S6_VGA_change/Proj/ColorBar.tan.rpt
S6_VGA_change/Proj/ColorBar.tan.summary
S6_VGA_change/Proj/ColorBar_assignment_defaults.qdf
S6_VGA_change/Proj/rom.bsf
S6_VGA_change/Proj/rom.v
S6_VGA_change/Proj/rom_8.bsf
S6_VGA_change/Proj/rom_8.v
S6_VGA_change/Proj/rom_8_bb.v
S6_VGA_change/Proj/rom_bb.v
S6_VGA_change/Proj/simulation/modelsim/ColorBar.vho
S6_VGA_change/Proj/simulation/modelsim/ColorBar.vo
S6_VGA_change/Proj/simulation/modelsim/ColorBar_modelsim.xrf
S6_VGA_change/Proj/simulation/modelsim/ColorBar_v.sdo
S6_VGA_change/Proj/simulation/modelsim/ColorBar_vhd.sdo
S6_VGA_change/Proj/simulation/modelsim/cyclone_atoms.v
S6_VGA_change/Proj/simulation/modelsim/vga_test.cr.mti
S6_VGA_change/Proj/simulation/modelsim/vga_test.mpf
S6_VGA_change/Proj/simulation/modelsim/vga_test.v
S6_VGA_change/Proj/simulation/modelsim/vga_vl.v
S6_VGA_change/Proj/simulation/modelsim/wave.do
S6_VGA_change/Proj/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/@color@bar/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/@color@bar/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/@color@bar/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_and1/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_and1/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_and1/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_and16/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_and16/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_and16/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_asmiblock/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_asmiblock/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_asmiblock/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_asynch_io/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_asynch_io/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_asynch_io/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_asynch_lcell/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_asynch_lcell/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_asynch_lcell/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_b17mux21/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_b17mux21/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_b17mux21/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_b5mux21/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_b5mux21/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_b5mux21/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_bmux21/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_bmux21/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_bmux21/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_crcblock/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_crcblock/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_crcblock/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_dffe/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_dffe/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_dffe/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_dll/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_dll/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_dll/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_io/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_io/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_io/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_jtag/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_jtag/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_jtag/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_latch/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_latch/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_latch/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim

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