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文件名称:fpga_frame

  • 所属分类:
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  • 上传时间:
    2012-11-16
  • 文件大小:
    1.93mb
  • 已下载:
    0次
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  • 下载说明:
    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

测试代码,利用fpga发送一帧一帧的raw视频,用于DSP接受和测试-Test code, using fpga send a raw video frame by frame, for receiving and testing of DSP
(系统自动生成,下载前可以参看下载内容)

下载文件列表

fpga_frame/auto_project.ipf
fpga_frame/auto_project_1.ipf
fpga_frame/capen_test.v
fpga_frame/capen_test_isim_beh.wdb
fpga_frame/clk200Mhz.v
fpga_frame/clk200Mhz_arwz.ucf
fpga_frame/clk25.v
fpga_frame/clk25Mhz.bmm
fpga_frame/clk25Mhz.v
fpga_frame/clk25Mhz_arwz.ucf
fpga_frame/clk25_arwz.ucf
fpga_frame/clkdiv.bgn
fpga_frame/clkdiv.bit
fpga_frame/clkdiv.bld
fpga_frame/clkdiv.cmd_log
fpga_frame/clkdiv.drc
fpga_frame/clkdiv.gise
fpga_frame/clkdiv.lso
fpga_frame/clkdiv.ncd
fpga_frame/clkdiv.ngc
fpga_frame/clkdiv.ngd
fpga_frame/clkdiv.ngr
fpga_frame/clkdiv.pad
fpga_frame/clkdiv.par
fpga_frame/clkdiv.pcf
fpga_frame/clkdiv.prj
fpga_frame/clkdiv.ptwx
fpga_frame/clkdiv.stx
fpga_frame/clkdiv.syr
fpga_frame/clkdiv.twr
fpga_frame/clkdiv.twx
fpga_frame/clkdiv.ucf
fpga_frame/clkdiv.unroutes
fpga_frame/clkdiv.ut
fpga_frame/clkdiv.v
fpga_frame/clkdiv.xise
fpga_frame/clkdiv.xpi
fpga_frame/clkdiv.xst
fpga_frame/clkdiv_bitgen.xwbt
fpga_frame/clkdiv_cs.blc
fpga_frame/clkdiv_cs.ngc
fpga_frame/clkdiv_envsettings.html
fpga_frame/clkdiv_guide.ncd
fpga_frame/clkdiv_map.map
fpga_frame/clkdiv_map.mrp
fpga_frame/clkdiv_map.ncd
fpga_frame/clkdiv_map.ngm
fpga_frame/clkdiv_map.xrpt
fpga_frame/clkdiv_ngdbuild.xrpt
fpga_frame/clkdiv_pad.csv
fpga_frame/clkdiv_pad.txt
fpga_frame/clkdiv_par.xrpt
fpga_frame/clkdiv_summary.html
fpga_frame/clkdiv_summary.xml
fpga_frame/clkdiv_test.v
fpga_frame/clkdiv_test_beh.prj
fpga_frame/clkdiv_test_isim_beh.exe
fpga_frame/clkdiv_test_isim_beh.wdb
fpga_frame/clkdiv_usage.xml
fpga_frame/clkdiv_xst.xrpt
fpga_frame/coregen.cgc
fpga_frame/coregen.cgp
fpga_frame/fuse.log
fpga_frame/ipcore_dir/clk200Mhz.cgc
fpga_frame/ipcore_dir/clk200Mhz.cgp
fpga_frame/ipcore_dir/clk200Mhz.v
fpga_frame/ipcore_dir/clk200Mhz.xaw
fpga_frame/ipcore_dir/clk200Mhz_arwz.ucf
fpga_frame/ipcore_dir/clk200Mhz_flist.txt
fpga_frame/ipcore_dir/clk200Mhz_readme.txt
fpga_frame/ipcore_dir/clk200Mhz_xmdf.tcl
fpga_frame/ipcore_dir/clk25.cgc
fpga_frame/ipcore_dir/clk25.cgp
fpga_frame/ipcore_dir/clk25.v
fpga_frame/ipcore_dir/clk25.xaw
fpga_frame/ipcore_dir/clk25Mhz.cgc
fpga_frame/ipcore_dir/clk25Mhz.cgp
fpga_frame/ipcore_dir/clk25Mhz.v
fpga_frame/ipcore_dir/clk25Mhz.xaw
fpga_frame/ipcore_dir/clk25Mhz_arwz.ucf
fpga_frame/ipcore_dir/clk25Mhz_flist.txt
fpga_frame/ipcore_dir/clk25Mhz_readme.txt
fpga_frame/ipcore_dir/clk25Mhz_xmdf.tcl
fpga_frame/ipcore_dir/clk25_arwz.ucf
fpga_frame/ipcore_dir/clk25_flist.txt
fpga_frame/ipcore_dir/clk25_readme.txt
fpga_frame/ipcore_dir/clk25_xmdf.tcl
fpga_frame/ipcore_dir/xaw2verilog.log
fpga_frame/iseconfig/clkdiv.projectmgr
fpga_frame/iseconfig/clkdiv.xreport
fpga_frame/isim/isim_usage_statistics.html
fpga_frame/isim/last_test_isim_beh.exe.sim/isimcrash.log
fpga_frame/isim/last_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
fpga_frame/isim/last_test_isim_beh.exe.sim/isimkernel.log
fpga_frame/isim/last_test_isim_beh.exe.sim/last_test_isim_beh.exe
fpga_frame/isim/last_test_isim_beh.exe.sim/netId.dat
fpga_frame/isim/last_test_isim_beh.exe.sim/tmp_save/_1
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000000739473194_2593380106.c
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000000739473194_2593380106.didat
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000000739473194_2593380106.nt.obj
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000002106904578_2297623829.c
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000002106904578_2297623829.didat
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000002106904578_2297623829.nt.obj
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000002699405962_0225263307.c
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000002699405962_0225263307.didat
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000002699405962_0225263307.nt.obj
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000003325971091_0465932072.c
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000003325971091_0465932072.didat
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000003325971091_0465932072.nt.obj
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000004236793345_1625843133.c
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000004236793345_1625843133.didat
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000004236793345_1625843133.nt.obj
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000004236793345_3897995058.c
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000004236793345_3897995058.didat
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000004236793345_3897995058.nt.obj
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000004254772212_2282143210.c
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000004254772212_2282143210.didat
fpga_frame/isim/last_test_isim_beh.exe.sim/unisims_ver/m_00000000004254772212_2282143210.nt.obj
fpga_frame/isim/last_test_isim_beh.exe.sim/work/last_test_isim_beh.exe_main.c
fpga_frame/isim/last_test_isim_beh.exe.sim/work/last_test_isim_beh.exe_mai

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