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文件名称:RS232_FIR

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    2012-11-16
  • 文件大小:
    197.85kb
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Quartus II was a development tool of CPLD / FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit descr iption which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer / Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis-Quartus II was a development tool of CPLD/FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit descr iption which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer/Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis
相关搜索: altera cpld schematic

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下载文件列表

RS232_FIR/
RS232_FIR/band.vwf
RS232_FIR/baud.bsf
RS232_FIR/baud.vhd
RS232_FIR/baud.vhd.bak
RS232_FIR/data_rom.bsf
RS232_FIR/data_rom.vhd
RS232_FIR/data_rom.vhd.bak
RS232_FIR/data_rom.vwf
RS232_FIR/db/
RS232_FIR/db/rs232_fir.db_info
RS232_FIR/db/rs232_fir.sld_design_entry.sci
RS232_FIR/dff8.bsf
RS232_FIR/dff8.vhd
RS232_FIR/dff8.vhd.bak
RS232_FIR/dff8.vwf
RS232_FIR/fir.bsf
RS232_FIR/fir.vhd
RS232_FIR/fir.vhd.bak
RS232_FIR/fir.vwf
RS232_FIR/fir1.vwf
RS232_FIR/fir_b.bdf
RS232_FIR/fir_b.bsf
RS232_FIR/fir_block.bsf
RS232_FIR/reciever.bsf
RS232_FIR/reciever.vhd
RS232_FIR/reciever.vhd.bak
RS232_FIR/reciever.vwf
RS232_FIR/rs232_fir.asm.rpt
RS232_FIR/rs232_fir.bdf
RS232_FIR/rs232_fir.cdf
RS232_FIR/rs232_fir.done
RS232_FIR/rs232_fir.dpf
RS232_FIR/rs232_fir.fit.rpt
RS232_FIR/rs232_fir.fit.smsg
RS232_FIR/rs232_fir.fit.summary
RS232_FIR/rs232_fir.flow.rpt
RS232_FIR/rs232_fir.map.rpt
RS232_FIR/rs232_fir.map.summary
RS232_FIR/rs232_fir.pin
RS232_FIR/rs232_fir.pof
RS232_FIR/rs232_fir.qpf
RS232_FIR/rs232_fir.qsf
RS232_FIR/rs232_fir.qws
RS232_FIR/rs232_fir.sim.rpt
RS232_FIR/rs232_fir.sof
RS232_FIR/rs232_fir.sta.rpt
RS232_FIR/rs232_fir.sta.summary
RS232_FIR/rs232_fir.tan.rpt
RS232_FIR/rs232_fir.tan.summary
RS232_FIR/rs232_fir_top.vwf
RS232_FIR/slow.bsf
RS232_FIR/slow.vhd
RS232_FIR/strobe_gen.vhd
RS232_FIR/strobe_gen.vhd.bak
RS232_FIR/tflop.vhd
RS232_FIR/top.bsf
RS232_FIR/top.vhd
RS232_FIR/top.vhd.bak
RS232_FIR/transfer.bsf
RS232_FIR/transfer.vhd
RS232_FIR/transfer.vhd.bak
RS232_FIR/transfer.vwf
RS232_FIR/undo_redo.txt

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