INTRODUCTION

§ The VHSIC Hardware Descr iption Language (VHDL) is an

industry standard language used to describe hardware from

the abstract to concrete level.

§ The language not only defines the syntax but also defines

very clear simulation semantics for each language construct.

§ It is strong typed language and is often verbose to write.

§ Provides extensive range of modeling capabilities,it is possible

to quickly assimilate a core subset of the language that is both

easy and simple to understand without learning the more

complex features.