文件名称:get-start-with-modulesim
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内含基于altera公司的FPGA芯片用modulesim仿真步骤,和详细实例,教会怎么使用modulesim仿真和编写testbench程序。-Altera FPGA-based embedded chip company with modulesim simulation steps, and detailed examples, how to use the church modulesim testbench simulation and preparation procedures.
相关搜索: testbench altera
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get start with modulesim.txt
simulation
simulation/modelsim
simulation/modelsim/de1_t1.sft
simulation/modelsim/de1_t1.vo
simulation/modelsim/de1_t1.vt
simulation/modelsim/de1_t1.vt.bak
simulation/modelsim/de1_t1_modelsim.xrf
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak1
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak2
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak3
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak4
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak5
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak6
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak7
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak8
simulation/modelsim/de1_t1_v.sdo
simulation/modelsim/modelsim.ini
simulation/modelsim/msim_transcript
simulation/modelsim/rtl_work
simulation/modelsim/rtl_work/@crt_clk_bps
simulation/modelsim/rtl_work/@crt_clk_bps/verilog.psm
simulation/modelsim/rtl_work/@crt_clk_bps/_primary.dat
simulation/modelsim/rtl_work/@crt_clk_bps/_primary.dbs
simulation/modelsim/rtl_work/@crt_clk_bps/_primary.vhd
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t/verilog.psm
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t/_primary.dat
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t/_primary.dbs
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t/_primary.vhd
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t_4
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t_4/verilog.psm
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t_4/_primary.dat
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t_4/_primary.dbs
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t_4/_primary.vhd
simulation/modelsim/rtl_work/@s@t@a@r@t_@t@x
simulation/modelsim/rtl_work/@s@t@a@r@t_@t@x/verilog.psm
simulation/modelsim/rtl_work/@s@t@a@r@t_@t@x/_primary.dat
simulation/modelsim/rtl_work/@s@t@a@r@t_@t@x/_primary.dbs
simulation/modelsim/rtl_work/@s@t@a@r@t_@t@x/_primary.vhd
simulation/modelsim/rtl_work/@uart_tx
simulation/modelsim/rtl_work/@uart_tx/verilog.psm
simulation/modelsim/rtl_work/@uart_tx/_primary.dat
simulation/modelsim/rtl_work/@uart_tx/_primary.dbs
simulation/modelsim/rtl_work/@uart_tx/_primary.vhd
simulation/modelsim/rtl_work/@v@g@a_controller
simulation/modelsim/rtl_work/@v@g@a_controller/verilog.psm
simulation/modelsim/rtl_work/@v@g@a_controller/_primary.dat
simulation/modelsim/rtl_work/@v@g@a_controller/_primary.dbs
simulation/modelsim/rtl_work/@v@g@a_controller/_primary.vhd
simulation/modelsim/rtl_work/de1_t1
simulation/modelsim/rtl_work/de1_t1/verilog.psm
simulation/modelsim/rtl_work/de1_t1/_primary.dat
simulation/modelsim/rtl_work/de1_t1/_primary.dbs
simulation/modelsim/rtl_work/de1_t1/_primary.vhd
simulation/modelsim/rtl_work/de1_t1_vlg_tst
simulation/modelsim/rtl_work/de1_t1_vlg_tst/verilog.psm
simulation/modelsim/rtl_work/de1_t1_vlg_tst/_primary.dat
simulation/modelsim/rtl_work/de1_t1_vlg_tst/_primary.dbs
simulation/modelsim/rtl_work/de1_t1_vlg_tst/_primary.vhd
simulation/modelsim/rtl_work/pll_control
simulation/modelsim/rtl_work/pll_control/verilog.psm
simulation/modelsim/rtl_work/pll_control/_primary.dat
simulation/modelsim/rtl_work/pll_control/_primary.dbs
simulation/modelsim/rtl_work/pll_control/_primary.vhd
simulation/modelsim/rtl_work/_info
simulation/modelsim/rtl_work/_temp
simulation/modelsim/rtl_work/_vmake
simulation/modelsim/vsim.wlf
simulation
simulation/modelsim
simulation/modelsim/de1_t1.sft
simulation/modelsim/de1_t1.vo
simulation/modelsim/de1_t1.vt
simulation/modelsim/de1_t1.vt.bak
simulation/modelsim/de1_t1_modelsim.xrf
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak1
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak2
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak3
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak4
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak5
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak6
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak7
simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak8
simulation/modelsim/de1_t1_v.sdo
simulation/modelsim/modelsim.ini
simulation/modelsim/msim_transcript
simulation/modelsim/rtl_work
simulation/modelsim/rtl_work/@crt_clk_bps
simulation/modelsim/rtl_work/@crt_clk_bps/verilog.psm
simulation/modelsim/rtl_work/@crt_clk_bps/_primary.dat
simulation/modelsim/rtl_work/@crt_clk_bps/_primary.dbs
simulation/modelsim/rtl_work/@crt_clk_bps/_primary.vhd
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t/verilog.psm
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t/_primary.dat
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t/_primary.dbs
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t/_primary.vhd
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t_4
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t_4/verilog.psm
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t_4/_primary.dat
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t_4/_primary.dbs
simulation/modelsim/rtl_work/@s@e@g7_@l@u@t_4/_primary.vhd
simulation/modelsim/rtl_work/@s@t@a@r@t_@t@x
simulation/modelsim/rtl_work/@s@t@a@r@t_@t@x/verilog.psm
simulation/modelsim/rtl_work/@s@t@a@r@t_@t@x/_primary.dat
simulation/modelsim/rtl_work/@s@t@a@r@t_@t@x/_primary.dbs
simulation/modelsim/rtl_work/@s@t@a@r@t_@t@x/_primary.vhd
simulation/modelsim/rtl_work/@uart_tx
simulation/modelsim/rtl_work/@uart_tx/verilog.psm
simulation/modelsim/rtl_work/@uart_tx/_primary.dat
simulation/modelsim/rtl_work/@uart_tx/_primary.dbs
simulation/modelsim/rtl_work/@uart_tx/_primary.vhd
simulation/modelsim/rtl_work/@v@g@a_controller
simulation/modelsim/rtl_work/@v@g@a_controller/verilog.psm
simulation/modelsim/rtl_work/@v@g@a_controller/_primary.dat
simulation/modelsim/rtl_work/@v@g@a_controller/_primary.dbs
simulation/modelsim/rtl_work/@v@g@a_controller/_primary.vhd
simulation/modelsim/rtl_work/de1_t1
simulation/modelsim/rtl_work/de1_t1/verilog.psm
simulation/modelsim/rtl_work/de1_t1/_primary.dat
simulation/modelsim/rtl_work/de1_t1/_primary.dbs
simulation/modelsim/rtl_work/de1_t1/_primary.vhd
simulation/modelsim/rtl_work/de1_t1_vlg_tst
simulation/modelsim/rtl_work/de1_t1_vlg_tst/verilog.psm
simulation/modelsim/rtl_work/de1_t1_vlg_tst/_primary.dat
simulation/modelsim/rtl_work/de1_t1_vlg_tst/_primary.dbs
simulation/modelsim/rtl_work/de1_t1_vlg_tst/_primary.vhd
simulation/modelsim/rtl_work/pll_control
simulation/modelsim/rtl_work/pll_control/verilog.psm
simulation/modelsim/rtl_work/pll_control/_primary.dat
simulation/modelsim/rtl_work/pll_control/_primary.dbs
simulation/modelsim/rtl_work/pll_control/_primary.vhd
simulation/modelsim/rtl_work/_info
simulation/modelsim/rtl_work/_temp
simulation/modelsim/rtl_work/_vmake
simulation/modelsim/vsim.wlf
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