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文件名称:hw2

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    613.01kb
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  • 提 供 者：
    vi***
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Using the VHDL Entry Method, design a logic circuit that behaves a 2-bit adder ( X + Y + CinOrBin ) with carry-in when the control input SubAddn is ‘0’ and behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with borrow-in when the control input SubAddn is ‘1’. -Using the VHDL Entry Method, design a logic circuit that behaves as a 2-bit adder ( X + Y + CinOrBin ) with carry-in when the control input SubAddn is ‘0’ and behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with borrow-in　when the control input SubAddn is ‘1’.
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下载文件列表

hw2\hw2design1\addsub.asm.rpt
hw2\hw2design1\addsub.done
hw2\hw2design1\addsub.fit.rpt
hw2\hw2design1\addsub.fit.summary
hw2\hw2design1\addsub.flow.rpt
hw2\hw2design1\addsub.map.rpt
hw2\hw2design1\addsub.map.summary
hw2\hw2design1\addsub.pin
hw2\hw2design1\addsub.pof
hw2\hw2design1\addsub.qpf
hw2\hw2design1\addsub.qsf
hw2\hw2design1\addsub.qws
hw2\hw2design1\addsub.sim.rpt
hw2\hw2design1\addsub.sof
hw2\hw2design1\addsub.tan.rpt
hw2\hw2design1\addsub.tan.summary
hw2\hw2design1\addsub.vhd
hw2\hw2design1\addsub.vwf
hw2\hw2design1\db\addsub.(0).cnf.cdb
hw2\hw2design1\db\addsub.(0).cnf.hdb
hw2\hw2design1\db\addsub.(1).cnf.cdb
hw2\hw2design1\db\addsub.(1).cnf.hdb
hw2\hw2design1\db\addsub.(2).cnf.cdb
hw2\hw2design1\db\addsub.(2).cnf.hdb
hw2\hw2design1\db\addsub.(3).cnf.cdb
hw2\hw2design1\db\addsub.(3).cnf.hdb
hw2\hw2design1\db\addsub.asm.qmsg
hw2\hw2design1\db\addsub.asm_labs.ddb
hw2\hw2design1\db\addsub.cbx.xml
hw2\hw2design1\db\addsub.cmp.bpm
hw2\hw2design1\db\addsub.cmp.cdb
hw2\hw2design1\db\addsub.cmp.ecobp
hw2\hw2design1\db\addsub.cmp.hdb
hw2\hw2design1\db\addsub.cmp.kpt
hw2\hw2design1\db\addsub.cmp.logdb
hw2\hw2design1\db\addsub.cmp.qrpt
hw2\hw2design1\db\addsub.cmp.rdb
hw2\hw2design1\db\addsub.cmp.tdb
hw2\hw2design1\db\addsub.cmp0.ddb
hw2\hw2design1\db\addsub.cmp_merge.kpt
hw2\hw2design1\db\addsub.db_info
hw2\hw2design1\db\addsub.eco.cdb
hw2\hw2design1\db\addsub.eds_overflow
hw2\hw2design1\db\addsub.fit.qmsg
hw2\hw2design1\db\addsub.fnsim.cdb
hw2\hw2design1\db\addsub.fnsim.hdb
hw2\hw2design1\db\addsub.fnsim.qmsg
hw2\hw2design1\db\addsub.hier_info
hw2\hw2design1\db\addsub.hif
hw2\hw2design1\db\addsub.map.bpm
hw2\hw2design1\db\addsub.map.cdb
hw2\hw2design1\db\addsub.map.ecobp
hw2\hw2design1\db\addsub.map.hdb
hw2\hw2design1\db\addsub.map.kpt
hw2\hw2design1\db\addsub.map.logdb
hw2\hw2design1\db\addsub.map.qmsg
hw2\hw2design1\db\addsub.map_bb.cdb
hw2\hw2design1\db\addsub.map_bb.hdb
hw2\hw2design1\db\addsub.map_bb.hdbx
hw2\hw2design1\db\addsub.map_bb.logdb
hw2\hw2design1\db\addsub.pre_map.cdb
hw2\hw2design1\db\addsub.pre_map.hdb
hw2\hw2design1\db\addsub.psp
hw2\hw2design1\db\addsub.rtlv.hdb
hw2\hw2design1\db\addsub.rtlv_sg.cdb
hw2\hw2design1\db\addsub.rtlv_sg_swap.cdb
hw2\hw2design1\db\addsub.sgdiff.cdb
hw2\hw2design1\db\addsub.sgdiff.hdb
hw2\hw2design1\db\addsub.sim.hdb
hw2\hw2design1\db\addsub.sim.qmsg
hw2\hw2design1\db\addsub.sim.rdb
hw2\hw2design1\db\addsub.simfam
hw2\hw2design1\db\addsub.sim_ori.vwf
hw2\hw2design1\db\addsub.sld_design_entry.sci
hw2\hw2design1\db\addsub.sld_design_entry_dsc.sci
hw2\hw2design1\db\addsub.syn_hier_info
hw2\hw2design1\db\addsub.tan.qmsg
hw2\hw2design1\db\addsub.tis_db_list.ddb
hw2\hw2design1\db\prev_cmp_addsub.asm.qmsg
hw2\hw2design1\db\prev_cmp_addsub.fit.qmsg
hw2\hw2design1\db\prev_cmp_addsub.map.qmsg
hw2\hw2design1\db\prev_cmp_addsub.qmsg
hw2\hw2design1\db\prev_cmp_addsub.sim.qmsg
hw2\hw2design1\db\prev_cmp_addsub.tan.qmsg
hw2\hw2design1\db\wed.wsf
hw2\hw2design1\halfadder.vhd
hw2\hw2design1\halfsub.vhd
hw2\hw2design1\incremental_db\compiled_partitions\addsub.root_partition.cmp.atm
hw2\hw2design1\incremental_db\compiled_partitions\addsub.root_partition.cmp.dfp
hw2\hw2design1\incremental_db\compiled_partitions\addsub.root_partition.cmp.hdbx
hw2\hw2design1\incremental_db\compiled_partitions\addsub.root_partition.cmp.kpt
hw2\hw2design1\incremental_db\compiled_partitions\addsub.root_partition.cmp.logdb
hw2\hw2design1\incremental_db\compiled_partitions\addsub.root_partition.cmp.rcf
hw2\hw2design1\incremental_db\compiled_partitions\addsub.root_partition.map.atm
hw2\hw2design1\incremental_db\compiled_partitions\addsub.root_partition.map.dpi
hw2\hw2design1\incremental_db\compiled_partitions\addsub.root_partition.map.hdbx
hw2\hw2design1\incremental_db\compiled_partitions\addsub.root_partition.map.kpt
hw2\hw2design1\incremental_db\README
hw2\hw2design1\mux2x1.vhd
hw2\hw2design1\printout\addsub functional waveform.pdf
hw2\hw2design1\printout\addsub.pdf
hw2\hw2design1\printout\Fitter Resource Usage Summary.pdf
hw2\hw2design1\printout\halfadder.pdf
hw2\hw2design1\printout\halfsub.pdf
hw2\hw2design1\printout\mux2x1.pdf
hw2\hw2design1\printout\tpd.pdf
hw2\hw2design2\addsub.asm.rpt
hw2\hw2design2\addsub.done
hw2\hw2design2\addsub.fit.rpt
hw2\hw2design2\addsub.fit.summary
hw2\hw2design2\addsub.flow.rpt
hw2\hw2design2\addsub.map.rpt
hw2\hw2design2\addsub.map.summary
hw2\hw2design2\addsub.pin
hw2\hw2design2\addsub.pof
hw2\hw2design2\addsub.qpf
hw2\hw2design2\addsub.qsf
hw2\hw2design2\addsub.qws
hw2\hw2design2\addsub.sim.rpt
hw2\hw2design2\addsub.sof
hw2\hw2design2\addsub.tan.rpt
hw2\hw2design2\addsub.tan.summary
hw2\hw2design2\addsub.vhd
hw2\hw2design2\addsub.vwf
hw2\hw2design2\addsub_package.vhd
hw2\hw2design2\db\addsub.(0).cnf.cdb
hw2\hw2design2\db\addsub.(0).cnf.hdb
hw2\hw2design2\db\addsub.(1).cnf.cdb
hw2\hw2design2\db\addsub.(1).cnf.hdb
hw2\hw2design2\db\addsub.(2).cnf.cdb
hw2\hw2design2\db\addsub.(2).cnf.hdb
hw2\hw2design2\db\addsub.(3).cnf.cdb
hw2\hw2design2\db\addsub.(3).cnf.hdb
hw2\hw2design2\db\addsub.(4).cnf.cdb
hw2\hw2design2\db\addsub.(4).cnf.hdb
hw2\hw2design2\db\addsub.(5).cnf.cdb
hw2\hw2design2\db

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