使用ModelSim进行设计仿真ModelSim为HDL仿真工具，我们可以利用该软件来实现对所设计的VHDL或Verilog程序进行仿真，支持IEEE常见的各种硬件描述语言标准。可以进行两种语言的混合仿真，但推荐大家只对一种语言仿真。ModelSim常见的版本分为ModelSim XE和ModelSim SE两种，ModelSim版本更新很快-Design simulation using ModelSim HDL simulator ModelSim is, we can use the software to achieve the program designed to simulate VHDL or Verilog, to support a variety of common IEEE standard hardware descr iption language. Mixture of two languages ​ ​ can be simulated, but recommend only one language simulation. Common version of ModelSim and ModelSim SE ModelSim XE is divided into two types, ModelSim version update soon