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文件名称:CoreSPI_21_eval

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    614.47kb
  • 已下载：
    0次
  • 提 供 者：
    任****
  • 相关连接：
    无
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修正介绍说明

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SPI IP核源码，包括Verilog和VHDL两种语言源码-SPI IP core source code, including the two languages ​ ​ Verilog and VHDL source code
相关搜索： SPI IP

(系统自动生成,下载前可以参看下载内容)

下载文件列表

CoreSPI_eval/
CoreSPI_eval/doc/
CoreSPI_eval/doc/CHANGES.txt
CoreSPI_eval/doc/CoreSPI_DS.pdf
CoreSPI_eval/doc/CoreSPI_RN.pdf
CoreSPI_eval/doc/CoreSPI_UG.pdf
CoreSPI_eval/sim/
CoreSPI_eval/sim/mti_full/
CoreSPI_eval/sim/mti_full/user/
CoreSPI_eval/sim/mti_full/user/work_vhdl/
CoreSPI_eval/sim/mti_full/user/work_vhdl/_info
CoreSPI_eval/sim/mti_full/user/work_vhdl/spi_master/
CoreSPI_eval/sim/mti_full/user/work_vhdl/spi_master/_primary.dat
CoreSPI_eval/sim/mti_full/user/work_vhdl/spi_master/behv.dat
CoreSPI_eval/sim/mti_full/user/work_vhdl/spi_master/behv.asm
CoreSPI_eval/sim/mti_full/user/work_vhdl/spi_slave/
CoreSPI_eval/sim/mti_full/user/work_vhdl/spi_slave/_primary.dat
CoreSPI_eval/sim/mti_full/user/work_vhdl/spi_slave/behv.dat
CoreSPI_eval/sim/mti_full/user/work_vhdl/spi_slave/behv.asm
CoreSPI_eval/sim/mti_full/user/work_vhdl/corespi/
CoreSPI_eval/sim/mti_full/user/work_vhdl/corespi/_primary.dat
CoreSPI_eval/sim/mti_full/user/work_vhdl/corespi/behv.dat
CoreSPI_eval/sim/mti_full/user/work_vhdl/corespi/behv.asm
CoreSPI_eval/sim/mti_full/user/work_vhdl/tb_vhdl/
CoreSPI_eval/sim/mti_full/user/work_vhdl/tb_vhdl/_primary.dat
CoreSPI_eval/sim/mti_full/user/work_vhdl/tb_vhdl/behv.dat
CoreSPI_eval/sim/mti_full/user/work_vhdl/tb_vhdl/behv.asm
CoreSPI_eval/sim/mti_full/user/corespi_lib/
CoreSPI_eval/sim/mti_full/user/corespi_lib/_info
CoreSPI_eval/sim/mti_full/user/corespi_lib/corespi_pkg/
CoreSPI_eval/sim/mti_full/user/corespi_lib/corespi_pkg/_primary.dat
CoreSPI_eval/sim/mti_full/user/corespi_lib/corespi_pkg/_vhdl.asm
CoreSPI_eval/sim/mti_full/user/corespi_lib/corespi_pkg/body.dat
CoreSPI_eval/sim/mti_full/user/corespi_lib/corespi_pkg/body.asm
CoreSPI_eval/sim/mti_full/user/work_vlog/
CoreSPI_eval/sim/mti_full/user/work_vlog/_info
CoreSPI_eval/sim/mti_full/user/work_vlog/spi_master/
CoreSPI_eval/sim/mti_full/user/work_vlog/spi_master/verilog.asm
CoreSPI_eval/sim/mti_full/user/work_vlog/spi_master/_primary.dat
CoreSPI_eval/sim/mti_full/user/work_vlog/spi_slave/
CoreSPI_eval/sim/mti_full/user/work_vlog/spi_slave/verilog.asm
CoreSPI_eval/sim/mti_full/user/work_vlog/spi_slave/_primary.dat
CoreSPI_eval/sim/mti_full/user/work_vlog/@c@o@r@e@s@p@i/
CoreSPI_eval/sim/mti_full/user/work_vlog/@c@o@r@e@s@p@i/_primary.vhd
CoreSPI_eval/sim/mti_full/user/work_vlog/@c@o@r@e@s@p@i/verilog.asm
CoreSPI_eval/sim/mti_full/user/work_vlog/@c@o@r@e@s@p@i/_primary.dat
CoreSPI_eval/sim/mti_full/user/work_vlog/tb_vlog/
CoreSPI_eval/sim/mti_full/user/work_vlog/tb_vlog/_primary.vhd
CoreSPI_eval/sim/mti_full/user/work_vlog/tb_vlog/verilog.asm
CoreSPI_eval/sim/mti_full/user/work_vlog/tb_vlog/_primary.dat
CoreSPI_eval/sim/mti_full/user/compvhdl.do
CoreSPI_eval/sim/mti_full/user/compvlog.do
CoreSPI_eval/sim/mti_full/user/refreshvhdl.do
CoreSPI_eval/sim/mti_full/user/refreshvlog.do
CoreSPI_eval/sim/mti_full/user/wavetb.do
CoreSPI_eval/sim/mti_full/user/runvhdl.do
CoreSPI_eval/sim/mti_full/user/runvlog.do
CoreSPI_eval/sim/mti_libero/
CoreSPI_eval/sim/mti_libero/user/
CoreSPI_eval/sim/mti_libero/user/work_vhdl/
CoreSPI_eval/sim/mti_libero/user/work_vhdl/_info
CoreSPI_eval/sim/mti_libero/user/work_vhdl/spi_master/
CoreSPI_eval/sim/mti_libero/user/work_vhdl/spi_master/_primary.dat
CoreSPI_eval/sim/mti_libero/user/work_vhdl/spi_master/behv.dat
CoreSPI_eval/sim/mti_libero/user/work_vhdl/spi_master/behv.psm
CoreSPI_eval/sim/mti_libero/user/work_vhdl/spi_slave/
CoreSPI_eval/sim/mti_libero/user/work_vhdl/spi_slave/_primary.dat
CoreSPI_eval/sim/mti_libero/user/work_vhdl/spi_slave/behv.dat
CoreSPI_eval/sim/mti_libero/user/work_vhdl/spi_slave/behv.psm
CoreSPI_eval/sim/mti_libero/user/work_vhdl/corespi/
CoreSPI_eval/sim/mti_libero/user/work_vhdl/corespi/_primary.dat
CoreSPI_eval/sim/mti_libero/user/work_vhdl/corespi/behv.dat
CoreSPI_eval/sim/mti_libero/user/work_vhdl/corespi/behv.psm
CoreSPI_eval/sim/mti_libero/user/work_vhdl/tb_vhdl/
CoreSPI_eval/sim/mti_libero/user/work_vhdl/tb_vhdl/_primary.dat
CoreSPI_eval/sim/mti_libero/user/work_vhdl/tb_vhdl/behv.dat
CoreSPI_eval/sim/mti_libero/user/work_vhdl/tb_vhdl/behv.psm
CoreSPI_eval/sim/mti_libero/user/corespi_lib/
CoreSPI_eval/sim/mti_libero/user/corespi_lib/_info
CoreSPI_eval/sim/mti_libero/user/corespi_lib/corespi_pkg/
CoreSPI_eval/sim/mti_libero/user/corespi_lib/corespi_pkg/_primary.dat
CoreSPI_eval/sim/mti_libero/user/corespi_lib/corespi_pkg/_vhdl.psm
CoreSPI_eval/sim/mti_libero/user/corespi_lib/corespi_pkg/body.dat
CoreSPI_eval/sim/mti_libero/user/corespi_lib/corespi_pkg/body.psm
CoreSPI_eval/sim/mti_libero/user/work_vlog/
CoreSPI_eval/sim/mti_libero/user/work_vlog/_info
CoreSPI_eval/sim/mti_libero/user/work_vlog/spi_master/
CoreSPI_eval/sim/mti_libero/user/work_vlog/spi_master/verilog.psm
CoreSPI_eval/sim/mti_libero/user/work_vlog/spi_master/_primary.dat
CoreSPI_eval/sim/mti_libero/user/work_vlog/spi_slave/
CoreSPI_eval/sim/mti_libero/user/work_vlog/spi_slave/verilog.psm
CoreSPI_eval/sim/mti_libero/user/work_vlog/spi_slave/_primary.dat
CoreSPI_eval/sim/mti_libero/user/work_vlog/@c@o@r@e@s@p@i/
CoreSPI_eval/sim/mti_libero/user/work_vlog/@c@o@r@e@s@p@i/_primary.vhd
CoreSPI_eval/sim/mti_libero/user/work_vlog/@c@o@r@e@s@p@i/verilo

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