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文件名称:f_add

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.26mb
  • 已下载：
    0次
  • 提 供 者：
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

EDA实验中的全加器的VHDL语言的实现，包含半加器、全加器、JK触发器、D触发器以及50m分频的源程序-EDA test full adder in VHDL language implementation, including the half adder, full adder, JK flip-flop, D flip-flop and the frequency of the source 50m
(系统自动生成,下载前可以参看下载内容)

下载文件列表

EDA shiyan/D1/D1.asm.rpt
EDA shiyan/D1/D1.done
EDA shiyan/D1/D1.fit.rpt
EDA shiyan/D1/D1.fit.smsg
EDA shiyan/D1/D1.fit.summary
EDA shiyan/D1/D1.flow.rpt
EDA shiyan/D1/D1.map.rpt
EDA shiyan/D1/D1.map.summary
EDA shiyan/D1/D1.pin
EDA shiyan/D1/D1.pof
EDA shiyan/D1/D1.qpf
EDA shiyan/D1/D1.qsf
EDA shiyan/D1/D1.qws
EDA shiyan/D1/D1.sim.rpt
EDA shiyan/D1/D1.sof
EDA shiyan/D1/D1.tan.rpt
EDA shiyan/D1/D1.tan.summary
EDA shiyan/D1/D1.vhd
EDA shiyan/D1/D1.vwf
EDA shiyan/D1/db/D1.(0).cnf.cdb
EDA shiyan/D1/db/D1.(0).cnf.hdb
EDA shiyan/D1/db/D1.asm.qmsg
EDA shiyan/D1/db/D1.asm_labs.ddb
EDA shiyan/D1/db/D1.cbx.xml
EDA shiyan/D1/db/D1.cmp.bpm
EDA shiyan/D1/db/D1.cmp.cdb
EDA shiyan/D1/db/D1.cmp.ecobp
EDA shiyan/D1/db/D1.cmp.hdb
EDA shiyan/D1/db/D1.cmp.logdb
EDA shiyan/D1/db/D1.cmp.rdb
EDA shiyan/D1/db/D1.cmp.tdb
EDA shiyan/D1/db/D1.cmp0.ddb
EDA shiyan/D1/db/D1.cmp_bb.cdb
EDA shiyan/D1/db/D1.cmp_bb.hdb
EDA shiyan/D1/db/D1.cmp_bb.logdb
EDA shiyan/D1/db/D1.cmp_bb.rcf
EDA shiyan/D1/db/D1.dbp
EDA shiyan/D1/db/D1.db_info
EDA shiyan/D1/db/D1.eco.cdb
EDA shiyan/D1/db/D1.eds_overflow
EDA shiyan/D1/db/D1.fit.qmsg
EDA shiyan/D1/db/D1.hier_info
EDA shiyan/D1/db/D1.hif
EDA shiyan/D1/db/D1.map.bpm
EDA shiyan/D1/db/D1.map.cdb
EDA shiyan/D1/db/D1.map.ecobp
EDA shiyan/D1/db/D1.map.hdb
EDA shiyan/D1/db/D1.map.logdb
EDA shiyan/D1/db/D1.map.qmsg
EDA shiyan/D1/db/D1.map_bb.cdb
EDA shiyan/D1/db/D1.map_bb.hdb
EDA shiyan/D1/db/D1.map_bb.logdb
EDA shiyan/D1/db/D1.pre_map.cdb
EDA shiyan/D1/db/D1.pre_map.hdb
EDA shiyan/D1/db/D1.psp
EDA shiyan/D1/db/D1.pss
EDA shiyan/D1/db/D1.rtlv.hdb
EDA shiyan/D1/db/D1.rtlv_sg.cdb
EDA shiyan/D1/db/D1.rtlv_sg_swap.cdb
EDA shiyan/D1/db/D1.sgdiff.cdb
EDA shiyan/D1/db/D1.sgdiff.hdb
EDA shiyan/D1/db/D1.signalprobe.cdb
EDA shiyan/D1/db/D1.sim.cvwf
EDA shiyan/D1/db/D1.sim.hdb
EDA shiyan/D1/db/D1.sim.qmsg
EDA shiyan/D1/db/D1.sim.rdb
EDA shiyan/D1/db/D1.sld_design_entry.sci
EDA shiyan/D1/db/D1.sld_design_entry_dsc.sci
EDA shiyan/D1/db/D1.syn_hier_info
EDA shiyan/D1/db/D1.tan.qmsg
EDA shiyan/D1/db/D1.tis_db_list.ddb
EDA shiyan/D1/db/prev_cmp_D1.asm.qmsg
EDA shiyan/D1/db/prev_cmp_D1.fit.qmsg
EDA shiyan/D1/db/prev_cmp_D1.map.qmsg
EDA shiyan/D1/db/prev_cmp_D1.qmsg
EDA shiyan/D1/db/prev_cmp_D1.sim.qmsg
EDA shiyan/D1/db/prev_cmp_D1.tan.qmsg
EDA shiyan/D1/db/wed.wsf
EDA shiyan/Fp28/db/Fp28.(0).cnf.cdb
EDA shiyan/Fp28/db/Fp28.(0).cnf.hdb
EDA shiyan/Fp28/db/Fp28.asm.qmsg
EDA shiyan/Fp28/db/Fp28.asm_labs.ddb
EDA shiyan/Fp28/db/Fp28.cbx.xml
EDA shiyan/Fp28/db/Fp28.cmp.bpm
EDA shiyan/Fp28/db/Fp28.cmp.cdb
EDA shiyan/Fp28/db/Fp28.cmp.ecobp
EDA shiyan/Fp28/db/Fp28.cmp.hdb
EDA shiyan/Fp28/db/Fp28.cmp.logdb
EDA shiyan/Fp28/db/Fp28.cmp.rdb
EDA shiyan/Fp28/db/Fp28.cmp.tdb
EDA shiyan/Fp28/db/Fp28.cmp0.ddb
EDA shiyan/Fp28/db/Fp28.cmp_bb.cdb
EDA shiyan/Fp28/db/Fp28.cmp_bb.hdb
EDA shiyan/Fp28/db/Fp28.cmp_bb.logdb
EDA shiyan/Fp28/db/Fp28.cmp_bb.rcf
EDA shiyan/Fp28/db/Fp28.dbp
EDA shiyan/Fp28/db/Fp28.db_info
EDA shiyan/Fp28/db/Fp28.eco.cdb
EDA shiyan/Fp28/db/Fp28.eds_overflow
EDA shiyan/Fp28/db/Fp28.fit.qmsg
EDA shiyan/Fp28/db/Fp28.hier_info
EDA shiyan/Fp28/db/Fp28.hif
EDA shiyan/Fp28/db/Fp28.map.bpm
EDA shiyan/Fp28/db/Fp28.map.cdb
EDA shiyan/Fp28/db/Fp28.map.ecobp
EDA shiyan/Fp28/db/Fp28.map.hdb
EDA shiyan/Fp28/db/Fp28.map.logdb
EDA shiyan/Fp28/db/Fp28.map.qmsg
EDA shiyan/Fp28/db/Fp28.map_bb.cdb
EDA shiyan/Fp28/db/Fp28.map_bb.hdb
EDA shiyan/Fp28/db/Fp28.map_bb.logdb
EDA shiyan/Fp28/db/Fp28.pre_map.cdb
EDA shiyan/Fp28/db/Fp28.pre_map.hdb
EDA shiyan/Fp28/db/Fp28.psp
EDA shiyan/Fp28/db/Fp28.pss
EDA shiyan/Fp28/db/Fp28.rtlv.hdb
EDA shiyan/Fp28/db/Fp28.rtlv_sg.cdb
EDA shiyan/Fp28/db/Fp28.rtlv_sg_swap.cdb
EDA shiyan/Fp28/db/Fp28.sgdiff.cdb
EDA shiyan/Fp28/db/Fp28.sgdiff.hdb
EDA shiyan/Fp28/db/Fp28.signalprobe.cdb
EDA shiyan/Fp28/db/Fp28.sim.cvwf
EDA shiyan/Fp28/db/Fp28.sim.hdb
EDA shiyan/Fp28/db/Fp28.sim.qmsg
EDA shiyan/Fp28/db/Fp28.sld_design_entry.sci
EDA shiyan/Fp28/db/Fp28.sld_design_entry_dsc.sci
EDA shiyan/Fp28/db/Fp28.syn_hier_info
EDA shiyan/Fp28/db/Fp28.tan.qmsg
EDA shiyan/Fp28/db/Fp28.tis_db_list.ddb
EDA shiyan/Fp28/db/prev_cmp_Fp28.qmsg
EDA shiyan/Fp28/db/prev_cmp_Fp28.sim.qmsg
EDA shiyan/Fp28/db/wed.wsf
EDA shiyan/Fp28/Fp28.asm.rpt
EDA shiyan/Fp28/Fp28.done
EDA shiyan/Fp28/Fp28.fit.rpt
EDA shiyan/Fp28/Fp28.fit.smsg
EDA shiyan/Fp28/Fp28.fit.summary
EDA shiyan/Fp28/Fp28.flow.rpt
EDA shiyan/Fp28/Fp28.map.rpt
EDA shiyan/Fp28/Fp28.map.summary
EDA shiyan/Fp28/Fp28.pin
EDA shiyan/Fp28/Fp28.pof
EDA shiyan/Fp28/Fp28.qpf
EDA shiyan/Fp28/Fp28.qsf
EDA shiyan/Fp28/Fp28.qws
EDA shiyan/Fp28/Fp28.sim.rpt
EDA shiyan/Fp28/Fp28.sof
EDA shiyan/Fp28/Fp28.tan.rpt
EDA shiyan/Fp28/Fp28.tan.summary
EDA shiyan/Fp28/Fp28.vhd
EDA shiyan/Fp28/Fp28.vhd.bak
EDA shiyan/Fp28/Fp28.vwf
EDA shiyan/f_adder/db/f_adder.(0).cnf.cdb
EDA shiyan/f_adder/db/f_adder.(0).cnf.hdb
EDA shiyan/f_adder/db/f_adder.(1).cnf.cdb
EDA shiyan/f_adder/db/f_adder.(1).cnf.hdb
EDA shiyan/f_adder/db/f_adder.(2).cnf.cdb
EDA shiyan/f_adder/db/f_adder.(2).cnf.hdb
EDA shiyan/f_adder/db/f_adder.asm.qmsg
EDA shiyan/f_adder/db/f_adder.asm_labs.ddb
EDA shiyan/f_adder/db/f_adder.cbx.xml
EDA shiyan/f_adder/db/f_adder.cmp.bpm
EDA s

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