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文件名称:verilogChapter-2

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    221.65kb
  • 已下载：
    0次
  • 提 供 者：
    Alice*****
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

续chapter01,给出了从入门到工程应用的一些实例，可以帮助初学者通过学习实例了解和掌握硬件描述语言的基本知识。-Continue chapter01, from entry to the project are given some examples of applications that can help beginners learn instance by hardware descr iption language to understand and master the basics.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Chapter-2/2.1/adder
Chapter-2/2.1/adder.cr.mti
Chapter-2/2.1/adder.mpf
Chapter-2/2.1/adder.v
Chapter-2/2.1/adder_testbench.v
Chapter-2/2.1/transcript
Chapter-2/2.1/vsim.wlf
Chapter-2/2.1/chart/Thumbs.db
Chapter-2/2.1/chart/嗾2-2.bmp
Chapter-2/2.1/chart/表2-1.bmp
Chapter-2/2.1/chart
Chapter-2/2.1/wave/Thumbs.db
Chapter-2/2.1/wave/adder.bmp
Chapter-2/2.1/wave/adder_testbench.bmp
Chapter-2/2.1/wave
Chapter-2/2.1/work/_info
Chapter-2/2.1/work/adder/_primary.dat
Chapter-2/2.1/work/adder/_primary.vhd
Chapter-2/2.1/work/adder/verilog.asm
Chapter-2/2.1/work/adder
Chapter-2/2.1/work/adder_testbench/_primary.dat
Chapter-2/2.1/work/adder_testbench/_primary.vhd
Chapter-2/2.1/work/adder_testbench/verilog.asm
Chapter-2/2.1/work/adder_testbench
Chapter-2/2.1/work
Chapter-2/2.1
Chapter-2/2.2/full_add.cr.mti
Chapter-2/2.2/full_add.mpf
Chapter-2/2.2/full_add.v
Chapter-2/2.2/full_add_testbench.v
Chapter-2/2.2/transcript
Chapter-2/2.2/vsim.wlf
Chapter-2/2.2/chart/Thumbs.db
Chapter-2/2.2/chart/嗾2-4.bmp
Chapter-2/2.2/chart/表2-2.bmp
Chapter-2/2.2/chart
Chapter-2/2.2/wave/Thumbs.db
Chapter-2/2.2/wave/full_add.bmp
Chapter-2/2.2/wave/full_add_testbench.bmp
Chapter-2/2.2/wave
Chapter-2/2.2/work/_info
Chapter-2/2.2/work/full_add/_primary.dat
Chapter-2/2.2/work/full_add/_primary.vhd
Chapter-2/2.2/work/full_add/verilog.asm
Chapter-2/2.2/work/full_add
Chapter-2/2.2/work/full_add_testbench/_primary.dat
Chapter-2/2.2/work/full_add_testbench/_primary.vhd
Chapter-2/2.2/work/full_add_testbench/verilog.asm
Chapter-2/2.2/work/full_add_testbench
Chapter-2/2.2/work
Chapter-2/2.2
Chapter-2/2.3/adder4.cr.mti
Chapter-2/2.3/adder4.mpf
Chapter-2/2.3/adder4.v
Chapter-2/2.3/adder4_testbench.v
Chapter-2/2.3/transcript
Chapter-2/2.3/vsim.wlf
Chapter-2/2.3/chart/Thumbs.db
Chapter-2/2.3/chart/嗾2-7.bmp
Chapter-2/2.3/chart
Chapter-2/2.3/wave/Thumbs.db
Chapter-2/2.3/wave/adder4.bmp
Chapter-2/2.3/wave/adder4_testbench.bmp
Chapter-2/2.3/wave
Chapter-2/2.3/work/_info
Chapter-2/2.3/work/adder4/_primary.dat
Chapter-2/2.3/work/adder4/_primary.vhd
Chapter-2/2.3/work/adder4/verilog.asm
Chapter-2/2.3/work/adder4
Chapter-2/2.3/work/adder4_testbench/_primary.dat
Chapter-2/2.3/work/adder4_testbench/_primary.vhd
Chapter-2/2.3/work/adder4_testbench/verilog.asm
Chapter-2/2.3/work/adder4_testbench
Chapter-2/2.3/work
Chapter-2/2.3
Chapter-2/2.4/coun4_testbench.v
Chapter-2/2.4/count4.cr.mti
Chapter-2/2.4/count4.mpf
Chapter-2/2.4/count4.v
Chapter-2/2.4/transcript
Chapter-2/2.4/vsim.wlf
Chapter-2/2.4/chart/Thumbs.db
Chapter-2/2.4/chart/嗾2-10.bmp
Chapter-2/2.4/chart
Chapter-2/2.4/wave/Thumbs.db
Chapter-2/2.4/wave/coun4.bmp
Chapter-2/2.4/wave/coun4_testbench.bmp
Chapter-2/2.4/wave
Chapter-2/2.4/work/_info
Chapter-2/2.4/work/coun4_testbench/_primary.dat
Chapter-2/2.4/work/coun4_testbench/_primary.vhd
Chapter-2/2.4/work/coun4_testbench/verilog.asm
Chapter-2/2.4/work/coun4_testbench
Chapter-2/2.4/work/count4/_primary.dat
Chapter-2/2.4/work/count4/_primary.vhd
Chapter-2/2.4/work/count4/verilog.asm
Chapter-2/2.4/work/count4
Chapter-2/2.4/work
Chapter-2/2.4
Chapter-2/2.5/count60.cr.mti
Chapter-2/2.5/count60.mpf
Chapter-2/2.5/count60.v
Chapter-2/2.5/count60_testbench.v
Chapter-2/2.5/transcript
Chapter-2/2.5/vsim.wlf
Chapter-2/2.5/chart/Thumbs.db
Chapter-2/2.5/chart/嗾2-12.bmp
Chapter-2/2.5/chart/表2-3.bmp
Chapter-2/2.5/chart
Chapter-2/2.5/wave/Thumbs.db
Chapter-2/2.5/wave/count60.bmp
Chapter-2/2.5/wave/count60_testbench.bmp
Chapter-2/2.5/wave
Chapter-2/2.5/work/_info
Chapter-2/2.5/work/count60/_primary.dat
Chapter-2/2.5/work/count60/_primary.vhd
Chapter-2/2.5/work/count60/verilog.asm
Chapter-2/2.5/work/count60
Chapter-2/2.5/work/count60_testbench/_primary.dat
Chapter-2/2.5/work/count60_testbench/_primary.vhd
Chapter-2/2.5/work/count60_testbench/verilog.asm
Chapter-2/2.5/work/count60_testbench
Chapter-2/2.5/work
Chapter-2/2.5
Chapter-2

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