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文件名称:verilogChapter-4

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    332.94kb
  • 已下载：
    0次
  • 提 供 者：
    Alice*****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

续chapter03,给出了从入门到工程应用的一些实例，可以帮助初学者通过学习实例了解和掌握硬件描述语言的基本知识。-Continued chapter03, from entry to the project are given some examples of applications that can help beginners learn instance by hardware descr iption language to understand and master the basics.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Chapter-4/4.1/bin_enc.cr.mti
Chapter-4/4.1/bin_enc.mpf
Chapter-4/4.1/bin_enc.v
Chapter-4/4.1/bin_enc_testbench.v
Chapter-4/4.1/transcript
Chapter-4/4.1/vsim.wlf
Chapter-4/4.1/chart/Thumbs.db
Chapter-4/4.1/chart/嗾4-2.bmp
Chapter-4/4.1/chart/表4-1.bmp
Chapter-4/4.1/chart
Chapter-4/4.1/wave/Thumbs.db
Chapter-4/4.1/wave/bin_enc.bmp
Chapter-4/4.1/wave/bin_enc_testbench.bmp
Chapter-4/4.1/wave
Chapter-4/4.1/work/_info
Chapter-4/4.1/work/bin_enc/_primary.dat
Chapter-4/4.1/work/bin_enc/_primary.vhd
Chapter-4/4.1/work/bin_enc/verilog.asm
Chapter-4/4.1/work/bin_enc
Chapter-4/4.1/work/bin_enc_testbench/_primary.dat
Chapter-4/4.1/work/bin_enc_testbench/_primary.vhd
Chapter-4/4.1/work/bin_enc_testbench/verilog.asm
Chapter-4/4.1/work/bin_enc_testbench
Chapter-4/4.1/work
Chapter-4/4.1
Chapter-4/4.2/manch_de.rpt
Chapter-4/4.2/manch_de.v
Chapter-4/4.2/manch_de_testbench.v
Chapter-4/4.2/manch_en.rpt
Chapter-4/4.2/manch_en.v
Chapter-4/4.2/manch_en_de.cr.mti
Chapter-4/4.2/manch_en_de.mpf
Chapter-4/4.2/manch_en_de.v
Chapter-4/4.2/manch_en_testbench.v
Chapter-4/4.2/transcript
Chapter-4/4.2/vsim.wlf
Chapter-4/4.2/chart/Thumbs.db
Chapter-4/4.2/chart/嗾4-5.bmp
Chapter-4/4.2/chart/嗾4-7.bmp
Chapter-4/4.2/chart
Chapter-4/4.2/wave/Thumbs.db
Chapter-4/4.2/wave/manch_de.bmp
Chapter-4/4.2/wave/manch_de_testbench.bmp
Chapter-4/4.2/wave/manch_en.bmp
Chapter-4/4.2/wave/manch_en_testbench.bmp
Chapter-4/4.2/wave
Chapter-4/4.2/work/_info
Chapter-4/4.2/work/manch_de/_primary.dat
Chapter-4/4.2/work/manch_de/_primary.vhd
Chapter-4/4.2/work/manch_de/verilog.asm
Chapter-4/4.2/work/manch_de
Chapter-4/4.2/work/manch_de_testbench/_primary.dat
Chapter-4/4.2/work/manch_de_testbench/_primary.vhd
Chapter-4/4.2/work/manch_de_testbench/verilog.asm
Chapter-4/4.2/work/manch_de_testbench
Chapter-4/4.2/work/manch_en/_primary.dat
Chapter-4/4.2/work/manch_en/_primary.vhd
Chapter-4/4.2/work/manch_en/verilog.asm
Chapter-4/4.2/work/manch_en
Chapter-4/4.2/work/manch_en_de/_primary.dat
Chapter-4/4.2/work/manch_en_de/_primary.vhd
Chapter-4/4.2/work/manch_en_de/verilog.asm
Chapter-4/4.2/work/manch_en_de
Chapter-4/4.2/work/manch_en_testbench/_primary.dat
Chapter-4/4.2/work/manch_en_testbench/_primary.vhd
Chapter-4/4.2/work/manch_en_testbench/verilog.asm
Chapter-4/4.2/work/manch_en_testbench
Chapter-4/4.2/work
Chapter-4/4.2
Chapter-4/4.3/Signal_detect.v
Chapter-4/4.3/decode.v
Chapter-4/4.3/decode_ter.rpt
Chapter-4/4.3/decode_testbench.v
Chapter-4/4.3/miller_de.cr.mti
Chapter-4/4.3/miller_de.mpf
Chapter-4/4.3/miller_de.v
Chapter-4/4.3/miller_de_testbench.v
Chapter-4/4.3/signal_detect_testbench.v
Chapter-4/4.3/signal_ter.rpt
Chapter-4/4.3/transcript
Chapter-4/4.3/vsim.wlf
Chapter-4/4.3/chart/Thumbs.db
Chapter-4/4.3/chart/嗾4-11.bmp
Chapter-4/4.3/chart/嗾4-13.bmp
Chapter-4/4.3/chart
Chapter-4/4.3/wave/Thumbs.db
Chapter-4/4.3/wave/decode.bmp
Chapter-4/4.3/wave/decode_testbench.bmp
Chapter-4/4.3/wave/miller_de.bmp
Chapter-4/4.3/wave/miller_de_testbench.bmp
Chapter-4/4.3/wave/signal_detect.bmp
Chapter-4/4.3/wave/signal_detect_testbench.bmp
Chapter-4/4.3/wave
Chapter-4/4.3/work/_info
Chapter-4/4.3/work/decode/_primary.dat
Chapter-4/4.3/work/decode/_primary.vhd
Chapter-4/4.3/work/decode/verilog.asm
Chapter-4/4.3/work/decode
Chapter-4/4.3/work/decode_testbench/_primary.dat
Chapter-4/4.3/work/decode_testbench/_primary.vhd
Chapter-4/4.3/work/decode_testbench/verilog.asm
Chapter-4/4.3/work/decode_testbench
Chapter-4/4.3/work/miller_de/_primary.dat
Chapter-4/4.3/work/miller_de/_primary.vhd
Chapter-4/4.3/work/miller_de/verilog.asm
Chapter-4/4.3/work/miller_de
Chapter-4/4.3/work/miller_de_testbench/_primary.dat
Chapter-4/4.3/work/miller_de_testbench/_primary.vhd
Chapter-4/4.3/work/miller_de_testbench/verilog.asm
Chapter-4/4.3/work/miller_de_testbench
Chapter-4/4.3/work/signal_detect/_primary.dat
Chapter-4/4.3/work/signal_detect/_primary.vhd
Chapter-4/4.3/work/signal_detect/verilog.asm
Chapter-4/4.3/work/signal_detect
Chapter-4/4.3/work/signal_detect_testbench/_primary.dat
Chapter-4/4.3/work/signal_detect_testbench/_primary.vhd
Chapter-4/4.3/work/signal_detect_testbench/verilog.asm
Chapter-4/4.3/work/signal_detect_testbench
Chapter-4/4.3/work
Chapter-4/4.3
Chapter-4

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