Verilog HDL作为一种规范的硬件描述语言,被广泛应用于电路的设计中。他的设计描述可被不同的工具所支持,可用不同器件来实现。利用Verilog HDL语言自顶向下的设计方法设计交通灯控制系统，使其实现道路交通的正常运转，突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点，并通过Xilinx ISE6.02和ModelSim5.6完成综合、仿真。此程序通过下载到FPGA芯片后,可应用于实际的交通灯控制系统中。-Verilog HDL as a standard hardware descr iption language, is widely used in circuit design. Descr iption of his design can be supported by different tools, different devices can be used to achieve. Using Verilog HDL language top-down design approach traffic light control system to achieve the normal operation of road transport, highlighting its good as a hardware descr iption language, readability, portability and ease of understanding, etc., and completed by Xilinx ISE6.02 and ModelSim5.6 synthesis, simulation. Through this program downloaded to the FPGA chip, can be applied to the actual traffic light control system.