vhdl实现cpu用verilog写的8位CPU源码，通过汇编语言可以实现加减乘左移右移等运算。并通过ASC流程可以模拟出其内部电路结构。代码，截图，readme在文件夹中-With 8-bit CPU to write verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. ASC process through its internal circuitry to simulate the structure. Code, screenshots, readme in the folder-cpu using verilog vhdl achieve 8-bit CPU to write source code, assembly language can be achieved through the addition and subtraction and other operations by the left right. And the process can be simulated by the ASC in its internal circuit structure. Code, screenshots, readme in the folder-With 8-bit CPU to write verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. ASC process through its internal circuitry to simulate the structure. Code, screenshots, readme in the folder