文件名称:add4
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- 上传时间:2012-11-16
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文件大小:127.4kb
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四位加法器verilog源代码,经过modelsim仿真验证正确,用ISE7.1i以上版本打开工程文件。-Four adder verilog source code, right after the modelsim simulation with ISE7.1i later open the project file.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
add4/
add4/__projnav/
add4/__projnav/add4.gfl
add4/__projnav/add4.xst
add4/__projnav/add4_flowplus.gfl
add4/__projnav/full_add1.xst
add4/__projnav/runXst_tcl.rsp
add4/__projnav/sumrpt_tcl.rsp
add4/__projnav.log
add4/_xmsgs/
add4/add4.cmd_log
add4/add4.dhp
add4/add4.ise
add4/add4.ise_ISE_Backup
add4/add4.lso
add4/add4.ngc
add4/add4.ngr
add4/add4.prj
add4/add4.stx
add4/add4.syr
add4/add4_summary.html
add4/add4_tbw.ant
add4/add4_tbw.fdo
add4/add4_tbw.tbw
add4/add4_tbw.tfw
add4/add4_tbw.udo
add4/add4_tbw.xwv
add4/add4_tbw.xwv_bak
add4/add4_tbw_bencher.prj
add4/add4_vhdl.prj
add4/adder4.v
add4/automake.log
add4/full_add1.cmd_log
add4/full_add1.lso
add4/full_add1.ngc
add4/full_add1.ngr
add4/full_add1.prj
add4/full_add1.stx
add4/full_add1.syr
add4/full_add1.v
add4/full_add1_summary.html
add4/full_add1_vhdl.prj
add4/results.txt
add4/transcript
add4/vsim.wlf
add4/work/
add4/work/_info
add4/work/_opt/
add4/work/_opt/_deps
add4/work/_opt/e__Xilinx_verilog_mti_se_XilinxCoreLib_ver__info
add4/work/_opt/e__Xilinx_verilog_mti_se_unisims_ver__info
add4/work/_opt/work__info
add4/work/_opt/work_add4_fast.dt2
add4/work/_opt/work_add4_tbw_fast.asm
add4/work/_opt/work_add4_tbw_fast.dt2
add4/work/_opt/work_full_add1_fast.dt2
add4/work/_opt/work_glbl_fast.asm
add4/work/_opt/work_glbl_fast.dt2
add4/work/_temp/
add4/work/add4/
add4/work/add4/_primary.dat
add4/work/add4/_primary.vhd
add4/work/add4/verilog.asm
add4/work/add4_tbw/
add4/work/add4_tbw/_primary.dat
add4/work/add4_tbw/_primary.vhd
add4/work/add4_tbw/verilog.asm
add4/work/full_add1/
add4/work/full_add1/_primary.dat
add4/work/full_add1/_primary.vhd
add4/work/full_add1/verilog.asm
add4/work/glbl/
add4/work/glbl/_primary.dat
add4/work/glbl/_primary.vhd
add4/xst/
add4/xst/dump.xst/
add4/xst/dump.xst/add4.prj/
add4/xst/dump.xst/add4.prj/ngx/
add4/xst/dump.xst/add4.prj/ngx/notopt/
add4/xst/dump.xst/add4.prj/ngx/opt/
add4/xst/dump.xst/full_add1.prj/
add4/xst/dump.xst/full_add1.prj/ngx/
add4/xst/dump.xst/full_add1.prj/ngx/notopt/
add4/xst/dump.xst/full_add1.prj/ngx/opt/
add4/xst/work/
add4/xst/work/hdllib.ref
add4/xst/work/vlg14/
add4/xst/work/vlg14/full__add1.bin
add4/xst/work/vlg49/
add4/xst/work/vlg49/add4.bin
add4/__projnav/
add4/__projnav/add4.gfl
add4/__projnav/add4.xst
add4/__projnav/add4_flowplus.gfl
add4/__projnav/full_add1.xst
add4/__projnav/runXst_tcl.rsp
add4/__projnav/sumrpt_tcl.rsp
add4/__projnav.log
add4/_xmsgs/
add4/add4.cmd_log
add4/add4.dhp
add4/add4.ise
add4/add4.ise_ISE_Backup
add4/add4.lso
add4/add4.ngc
add4/add4.ngr
add4/add4.prj
add4/add4.stx
add4/add4.syr
add4/add4_summary.html
add4/add4_tbw.ant
add4/add4_tbw.fdo
add4/add4_tbw.tbw
add4/add4_tbw.tfw
add4/add4_tbw.udo
add4/add4_tbw.xwv
add4/add4_tbw.xwv_bak
add4/add4_tbw_bencher.prj
add4/add4_vhdl.prj
add4/adder4.v
add4/automake.log
add4/full_add1.cmd_log
add4/full_add1.lso
add4/full_add1.ngc
add4/full_add1.ngr
add4/full_add1.prj
add4/full_add1.stx
add4/full_add1.syr
add4/full_add1.v
add4/full_add1_summary.html
add4/full_add1_vhdl.prj
add4/results.txt
add4/transcript
add4/vsim.wlf
add4/work/
add4/work/_info
add4/work/_opt/
add4/work/_opt/_deps
add4/work/_opt/e__Xilinx_verilog_mti_se_XilinxCoreLib_ver__info
add4/work/_opt/e__Xilinx_verilog_mti_se_unisims_ver__info
add4/work/_opt/work__info
add4/work/_opt/work_add4_fast.dt2
add4/work/_opt/work_add4_tbw_fast.asm
add4/work/_opt/work_add4_tbw_fast.dt2
add4/work/_opt/work_full_add1_fast.dt2
add4/work/_opt/work_glbl_fast.asm
add4/work/_opt/work_glbl_fast.dt2
add4/work/_temp/
add4/work/add4/
add4/work/add4/_primary.dat
add4/work/add4/_primary.vhd
add4/work/add4/verilog.asm
add4/work/add4_tbw/
add4/work/add4_tbw/_primary.dat
add4/work/add4_tbw/_primary.vhd
add4/work/add4_tbw/verilog.asm
add4/work/full_add1/
add4/work/full_add1/_primary.dat
add4/work/full_add1/_primary.vhd
add4/work/full_add1/verilog.asm
add4/work/glbl/
add4/work/glbl/_primary.dat
add4/work/glbl/_primary.vhd
add4/xst/
add4/xst/dump.xst/
add4/xst/dump.xst/add4.prj/
add4/xst/dump.xst/add4.prj/ngx/
add4/xst/dump.xst/add4.prj/ngx/notopt/
add4/xst/dump.xst/add4.prj/ngx/opt/
add4/xst/dump.xst/full_add1.prj/
add4/xst/dump.xst/full_add1.prj/ngx/
add4/xst/dump.xst/full_add1.prj/ngx/notopt/
add4/xst/dump.xst/full_add1.prj/ngx/opt/
add4/xst/work/
add4/xst/work/hdllib.ref
add4/xst/work/vlg14/
add4/xst/work/vlg14/full__add1.bin
add4/xst/work/vlg49/
add4/xst/work/vlg49/add4.bin
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