文件名称:fre_counter
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- 上传时间：2012-11-16
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文件大小：54.98kb
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用verilog实现的确数字频率计,内部含有各个功能模块-Verilog implementation is actually using digital frequency meter
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下载文件列表
fre_counter/clk_gen.v
fre_counter/count.v
fre_counter/count_4units.v
fre_counter/fre_counter.cr.mti
fre_counter/fre_counter.mpf
fre_counter/fre_counter.v
fre_counter/led_sel.v
fre_counter/top_sim.v
fre_counter/transform.v
fre_counter/vsim.wlf
fre_counter/wave.do
fre_counter/work/clk_gen/verilog.asm
fre_counter/work/clk_gen/_primary.dat
fre_counter/work/clk_gen/_primary.vhd
fre_counter/work/clk_gen
fre_counter/work/count/verilog.asm
fre_counter/work/count/_primary.dat
fre_counter/work/count/_primary.vhd
fre_counter/work/count
fre_counter/work/count_4units/verilog.asm
fre_counter/work/count_4units/_primary.dat
fre_counter/work/count_4units/_primary.vhd
fre_counter/work/count_4units
fre_counter/work/fre_counter/verilog.asm
fre_counter/work/fre_counter/_primary.dat
fre_counter/work/fre_counter/_primary.vhd
fre_counter/work/fre_counter
fre_counter/work/led_sel/verilog.asm
fre_counter/work/led_sel/_primary.dat
fre_counter/work/led_sel/_primary.vhd
fre_counter/work/led_sel
fre_counter/work/top_sim/verilog.asm
fre_counter/work/top_sim/_primary.dat
fre_counter/work/top_sim/_primary.vhd
fre_counter/work/top_sim
fre_counter/work/transform/verilog.asm
fre_counter/work/transform/_primary.dat
fre_counter/work/transform/_primary.vhd
fre_counter/work/transform
fre_counter/work/_info
fre_counter/work
fre_counter
fre_counter/count.v
fre_counter/count_4units.v
fre_counter/fre_counter.cr.mti
fre_counter/fre_counter.mpf
fre_counter/fre_counter.v
fre_counter/led_sel.v
fre_counter/top_sim.v
fre_counter/transform.v
fre_counter/vsim.wlf
fre_counter/wave.do
fre_counter/work/clk_gen/verilog.asm
fre_counter/work/clk_gen/_primary.dat
fre_counter/work/clk_gen/_primary.vhd
fre_counter/work/clk_gen
fre_counter/work/count/verilog.asm
fre_counter/work/count/_primary.dat
fre_counter/work/count/_primary.vhd
fre_counter/work/count
fre_counter/work/count_4units/verilog.asm
fre_counter/work/count_4units/_primary.dat
fre_counter/work/count_4units/_primary.vhd
fre_counter/work/count_4units
fre_counter/work/fre_counter/verilog.asm
fre_counter/work/fre_counter/_primary.dat
fre_counter/work/fre_counter/_primary.vhd
fre_counter/work/fre_counter
fre_counter/work/led_sel/verilog.asm
fre_counter/work/led_sel/_primary.dat
fre_counter/work/led_sel/_primary.vhd
fre_counter/work/led_sel
fre_counter/work/top_sim/verilog.asm
fre_counter/work/top_sim/_primary.dat
fre_counter/work/top_sim/_primary.vhd
fre_counter/work/top_sim
fre_counter/work/transform/verilog.asm
fre_counter/work/transform/_primary.dat
fre_counter/work/transform/_primary.vhd
fre_counter/work/transform
fre_counter/work/_info
fre_counter/work
fre_counter
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