FlashROM/FlashROM实验例程.pdf
FlashROM/Flash_ROM/designer/impl1/designer.log
FlashROM/Flash_ROM/designer/impl1/RDROM_top/projectData/RDROM_top.stp
FlashROM/Flash_ROM/designer/impl1/RDROM_top/RDROM_top.log
FlashROM/Flash_ROM/designer/impl1/RDROM_top/RDROM_top.pro
FlashROM/Flash_ROM/designer/impl1/RDROM_top.adb
FlashROM/Flash_ROM/designer/impl1/RDROM_top.dtf/verify.log
FlashROM/Flash_ROM/designer/impl1/RDROM_top.ide_des
FlashROM/Flash_ROM/designer/impl1/RDROM_top.lok
FlashROM/Flash_ROM/designer/impl1/RDROM_top.stp
FlashROM/Flash_ROM/designer/impl1/RDROM_top.tcl
FlashROM/Flash_ROM/designer/impl1/simulation/postlayout/@r@d@r@o@m_top/verilog.psm
FlashROM/Flash_ROM/designer/impl1/simulation/postlayout/@r@d@r@o@m_top/_primary.dat
FlashROM/Flash_ROM/designer/impl1/simulation/postlayout/@r@d@r@o@m_top/_primary.vhd
FlashROM/Flash_ROM/designer/impl1/simulation/postlayout/stimulus/verilog.psm
FlashROM/Flash_ROM/designer/impl1/simulation/postlayout/stimulus/_primary.dat
FlashROM/Flash_ROM/designer/impl1/simulation/postlayout/stimulus/_primary.vhd
FlashROM/Flash_ROM/designer/impl1/simulation/postlayout/tb_clock_minmax/verilog.psm
FlashROM/Flash_ROM/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dat
FlashROM/Flash_ROM/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.vhd
FlashROM/Flash_ROM/designer/impl1/simulation/postlayout/testbench/verilog.psm
FlashROM/Flash_ROM/designer/impl1/simulation/postlayout/testbench/_primary.dat
FlashROM/Flash_ROM/designer/impl1/simulation/postlayout/testbench/_primary.vhd
FlashROM/Flash_ROM/designer/impl1/simulation/postlayout/_info
FlashROM/Flash_ROM/Flash_ROM.prj
FlashROM/Flash_ROM/hdl/ctrl_ROM.v
FlashROM/Flash_ROM/hdl/RDROM_top.v
FlashROM/Flash_ROM/hdl/send.v
FlashROM/Flash_ROM/hdl/Sim_top.v
FlashROM/Flash_ROM/simulation/flashROM.mem
FlashROM/Flash_ROM/simulation/meminit.dat
FlashROM/Flash_ROM/simulation/modelsim.ini
FlashROM/Flash_ROM/simulation/modelsim.ini.sav
FlashROM/Flash_ROM/simulation/modelsim.log
FlashROM/Flash_ROM/simulation/presynth/@r@d@r@o@m_top/verilog.psm
FlashROM/Flash_ROM/simulation/presynth/@r@d@r@o@m_top/_primary.dat
FlashROM/Flash_ROM/simulation/presynth/@r@d@r@o@m_top/_primary.vhd
FlashROM/Flash_ROM/simulation/presynth/@sim_top/verilog.psm
FlashROM/Flash_ROM/simulation/presynth/@sim_top/_primary.dat
FlashROM/Flash_ROM/simulation/presynth/@sim_top/_primary.vhd
FlashROM/Flash_ROM/simulation/presynth/ctrl_@r@o@m/verilog.psm
FlashROM/Flash_ROM/simulation/presynth/ctrl_@r@o@m/_primary.dat
FlashROM/Flash_ROM/simulation/presynth/ctrl_@r@o@m/_primary.vhd
FlashROM/Flash_ROM/simulation/presynth/flash@r@o@m/verilog.psm
FlashROM/Flash_ROM/simulation/presynth/flash@r@o@m/_primary.dat
FlashROM/Flash_ROM/simulation/presynth/flash@r@o@m/_primary.vhd
FlashROM/Flash_ROM/simulation/presynth/send/verilog.psm
FlashROM/Flash_ROM/simulation/presynth/send/_primary.dat
FlashROM/Flash_ROM/simulation/presynth/send/_primary.vhd
FlashROM/Flash_ROM/simulation/presynth/stimulus/verilog.psm
FlashROM/Flash_ROM/simulation/presynth/stimulus/_primary.dat
FlashROM/Flash_ROM/simulation/presynth/stimulus/_primary.vhd
FlashROM/Flash_ROM/simulation/presynth/tb_clock_minmax/verilog.psm
FlashROM/Flash_ROM/simulation/presynth/tb_clock_minmax/_primary.dat
FlashROM/Flash_ROM/simulation/presynth/tb_clock_minmax/_primary.vhd
FlashROM/Flash_ROM/simulation/presynth/testbench/verilog.psm
FlashROM/Flash_ROM/simulation/presynth/testbench/_primary.dat
FlashROM/Flash_ROM/simulation/presynth/testbench/_primary.vhd
FlashROM/Flash_ROM/simulation/presynth/_info
FlashROM/Flash_ROM/simulation/run.do
FlashROM/Flash_ROM/simulation/vsim.wlf
FlashROM/Flash_ROM/simulation/wave.do
FlashROM/Flash_ROM/smartgen/flashROM/flashROM.cxf
FlashROM/Flash_ROM/smartgen/flashROM/flashROM.gen
FlashROM/Flash_ROM/smartgen/flashROM/flashROM.log
FlashROM/Flash_ROM/smartgen/flashROM/flashROM.mem
FlashROM/Flash_ROM/smartgen/flashROM/flashROM.ufc
FlashROM/Flash_ROM/smartgen/flashROM/flashROM.v
FlashROM/Flash_ROM/smartgen/flashROM_work.ixf
FlashROM/Flash_ROM/smartgen/smartgen.aws
FlashROM/Flash_ROM/stimulus/BtimErrors.log
FlashROM/Flash_ROM/stimulus/files_to_build.txt
FlashROM/Flash_ROM/stimulus/RDROM_top.dsk
FlashROM/Flash_ROM/stimulus/RDROM_top.hpj
FlashROM/Flash_ROM/stimulus/RDROM_top_tbench.bk
FlashROM/Flash_ROM/stimulus/RDROM_top_tbench.btim
FlashROM/Flash_ROM/stimulus/RDROM_top_tbench.v
FlashROM/Flash_ROM/stimulus/waveperl.log
FlashROM/Flash_ROM/synthesis/.recordref
FlashROM/Flash_ROM/synthesis/RDROM_top.areasrr
FlashROM/Flash_ROM/synthesis/RDROM_top.edn
FlashROM/Flash_ROM/synthesis/RDROM_top.fse
FlashROM/Flash_ROM/synthesis/RDROM_top.htm
FlashROM/Flash_ROM/synthesis/RDROM_top.map
FlashROM/Flash_ROM/synthesis/RDROM_top.sap
FlashROM/Flash_ROM/synthesis/RDROM_top.sdf
FlashROM/Flash_ROM/synthesis/RDROM_top.srd
FlashROM/Flash_ROM/synthesis/RDROM_top.srm
FlashROM/Flash_ROM/synthesis/RDROM_top.srr
FlashROM/Flash_ROM/synthesis/RDROM_top.srs
FlashROM/Flash_ROM/synthesis/RDROM_top.tlg
FlashROM/Flash_ROM/synthesis/RDROM_top_sdc.sdc
FlashROM/Flash_ROM/synthesis/RDROM_top_syn.prj
FlashROM/Flash_ROM/synthesis/stdout.log
FlashROM/Flash_ROM/synthesis/syntmp/R