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文件名称:Pipelined-MIPS

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    179.22kb
  • 已下载：
    0次
  • 提 供 者：
    t****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

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MIPS架构5级流水线设计，支持常用的整数指令。-5-stage pipeline MIPS architecture designed to support common integer instructions.
相关搜索： MIPS 5 STAGE PIPELINE

(系统自动生成,下载前可以参看下载内容)

下载文件列表

Pipelined MIPS/resource/alu.v
Pipelined MIPS/resource/alu_dec.v
Pipelined MIPS/resource/arithmetic_unit.v
Pipelined MIPS/resource/control_unit.v
Pipelined MIPS/resource/data_path.v
Pipelined MIPS/resource/dec.v
Pipelined MIPS/resource/equal.v
Pipelined MIPS/resource/full_adder.v
Pipelined MIPS/resource/hazard_unit.v
Pipelined MIPS/resource/imm_extension.v
Pipelined MIPS/resource/instr_reg.v
Pipelined MIPS/resource/logic_unit.v
Pipelined MIPS/resource/main_dec.v
Pipelined MIPS/resource/mux2.v
Pipelined MIPS/resource/mux3.v
Pipelined MIPS/resource/pc_adder.v
Pipelined MIPS/resource/regfile.v
Pipelined MIPS/resource/reg_.v
Pipelined MIPS/resource/reg_en.v
Pipelined MIPS/simulation/Pipeline MIPS.cr.mti
Pipelined MIPS/simulation/Pipeline MIPS.mpf
Pipelined MIPS/simulation/vish_stacktrace.vstf
Pipelined MIPS/simulation/vsim.wlf
Pipelined MIPS/simulation/work/alu/verilog.asm
Pipelined MIPS/simulation/work/alu/verilog.rw
Pipelined MIPS/simulation/work/alu/_primary.dat
Pipelined MIPS/simulation/work/alu/_primary.dbs
Pipelined MIPS/simulation/work/alu/_primary.vhd
Pipelined MIPS/simulation/work/alu_dec/verilog.asm
Pipelined MIPS/simulation/work/alu_dec/verilog.rw
Pipelined MIPS/simulation/work/alu_dec/_primary.dat
Pipelined MIPS/simulation/work/alu_dec/_primary.dbs
Pipelined MIPS/simulation/work/alu_dec/_primary.vhd
Pipelined MIPS/simulation/work/arithmetic_unit/verilog.asm
Pipelined MIPS/simulation/work/arithmetic_unit/verilog.rw
Pipelined MIPS/simulation/work/arithmetic_unit/_primary.dat
Pipelined MIPS/simulation/work/arithmetic_unit/_primary.dbs
Pipelined MIPS/simulation/work/arithmetic_unit/_primary.vhd
Pipelined MIPS/simulation/work/control_unit/verilog.asm
Pipelined MIPS/simulation/work/control_unit/verilog.rw
Pipelined MIPS/simulation/work/control_unit/_primary.dat
Pipelined MIPS/simulation/work/control_unit/_primary.dbs
Pipelined MIPS/simulation/work/control_unit/_primary.vhd
Pipelined MIPS/simulation/work/data_memory/verilog.asm
Pipelined MIPS/simulation/work/data_memory/verilog.rw
Pipelined MIPS/simulation/work/data_memory/_primary.dat
Pipelined MIPS/simulation/work/data_memory/_primary.dbs
Pipelined MIPS/simulation/work/data_memory/_primary.vhd
Pipelined MIPS/simulation/work/data_path/verilog.asm
Pipelined MIPS/simulation/work/data_path/verilog.rw
Pipelined MIPS/simulation/work/data_path/_primary.dat
Pipelined MIPS/simulation/work/data_path/_primary.dbs
Pipelined MIPS/simulation/work/data_path/_primary.vhd
Pipelined MIPS/simulation/work/dec/verilog.asm
Pipelined MIPS/simulation/work/dec/verilog.rw
Pipelined MIPS/simulation/work/dec/_primary.dat
Pipelined MIPS/simulation/work/dec/_primary.dbs
Pipelined MIPS/simulation/work/dec/_primary.vhd
Pipelined MIPS/simulation/work/equal/verilog.asm
Pipelined MIPS/simulation/work/equal/verilog.rw
Pipelined MIPS/simulation/work/equal/_primary.dat
Pipelined MIPS/simulation/work/equal/_primary.dbs
Pipelined MIPS/simulation/work/equal/_primary.vhd
Pipelined MIPS/simulation/work/full_adder/verilog.asm
Pipelined MIPS/simulation/work/full_adder/verilog.rw
Pipelined MIPS/simulation/work/full_adder/_primary.dat
Pipelined MIPS/simulation/work/full_adder/_primary.dbs
Pipelined MIPS/simulation/work/full_adder/_primary.vhd
Pipelined MIPS/simulation/work/hazard_unit/verilog.asm
Pipelined MIPS/simulation/work/hazard_unit/verilog.rw
Pipelined MIPS/simulation/work/hazard_unit/_primary.dat
Pipelined MIPS/simulation/work/hazard_unit/_primary.dbs
Pipelined MIPS/simulation/work/hazard_unit/_primary.vhd
Pipelined MIPS/simulation/work/imm_extension/verilog.asm
Pipelined MIPS/simulation/work/imm_extension/verilog.rw
Pipelined MIPS/simulation/work/imm_extension/_primary.dat
Pipelined MIPS/simulation/work/imm_extension/_primary.dbs
Pipelined MIPS/simulation/work/imm_extension/_primary.vhd
Pipelined MIPS/simulation/work/instruction_memory/verilog.asm
Pipelined MIPS/simulation/work/instruction_memory/verilog.rw
Pipelined MIPS/simulation/work/instruction_memory/_primary.dat
Pipelined MIPS/simulation/work/instruction_memory/_primary.dbs
Pipelined MIPS/simulation/work/instruction_memory/_primary.vhd
Pipelined MIPS/simulation/work/instr_reg/verilog.asm
Pipelined MIPS/simulation/work/instr_reg/verilog.rw
Pipelined MIPS/simulation/work/instr_reg/_primary.dat
Pipelined MIPS/simulation/work/instr_reg/_primary.dbs
Pipelined MIPS/simulation/work/instr_reg/_primary.vhd
Pipelined MIPS/simulation/work/logic_unit/verilog.asm
Pipelined MIPS/simulation/work/logic_unit/verilog.rw
Pipelined MIPS/simulation/work/logic_unit/_primary.dat
Pipelined MIPS/simulation/work/logic_unit/_primary.dbs
Pipelined MIPS/simulation/work/logic_unit/_primary.vhd
Pipelined MIPS/simulation/work/main_dec/verilog.asm
Pipelined MIPS/simulation/work/main_dec/verilog.rw
Pipelined MIPS/simulation/work/main_dec/_primary.dat
Pipelined MIPS/simulation/work/main_dec/_primary.dbs
Pipelined MIPS/simulation/work/main_dec/_primary.vhd
Pipelined MIPS/simulation/work/mips/verilog.asm
Pipelined MIPS/simulation/work/mips/verilog.rw
Pipelined MIPS/simulation/work/mips/_primary.dat
Pipelined MIPS/simulation/work/mips/_primary.dbs
Pipelined MIPS/simulation/work/mips/_primar

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