文件名称:test
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- 上传时间：2012-11-16
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文件大小：21.72kb
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一个进位计数器的简单verlag实现，仿真无误-A simple binary counter verlag achieved, the simulation is correct ... ...
(系统自动生成,下载前可以参看下载内容)
下载文件列表
test/modelsim.ini
test/tb_carry_counter.v
test/tb_carry_counter.v.bak
test/trigger_carry_counter.v
test/trigger_carry_counter.v.bak
test/vsim.wlf
test/work/@d_@f@f/verilog.asm
test/work/@d_@f@f/_primary.dat
test/work/@d_@f@f/_primary.vhd
test/work/@t_@f@f/verilog.asm
test/work/@t_@f@f/_primary.dat
test/work/@t_@f@f/_primary.vhd
test/work/ripple_carry_counter/verilog.asm
test/work/ripple_carry_counter/_primary.dat
test/work/ripple_carry_counter/_primary.vhd
test/work/stimulus/verilog.asm
test/work/stimulus/_primary.dat
test/work/stimulus/_primary.vhd
test/work/_info
test/work/@d_@f@f
test/work/@t_@f@f
test/work/ripple_carry_counter
test/work/stimulus
test/work
test
test/tb_carry_counter.v
test/tb_carry_counter.v.bak
test/trigger_carry_counter.v
test/trigger_carry_counter.v.bak
test/vsim.wlf
test/work/@d_@f@f/verilog.asm
test/work/@d_@f@f/_primary.dat
test/work/@d_@f@f/_primary.vhd
test/work/@t_@f@f/verilog.asm
test/work/@t_@f@f/_primary.dat
test/work/@t_@f@f/_primary.vhd
test/work/ripple_carry_counter/verilog.asm
test/work/ripple_carry_counter/_primary.dat
test/work/ripple_carry_counter/_primary.vhd
test/work/stimulus/verilog.asm
test/work/stimulus/_primary.dat
test/work/stimulus/_primary.vhd
test/work/_info
test/work/@d_@f@f
test/work/@t_@f@f
test/work/ripple_carry_counter
test/work/stimulus
test/work
test
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