本实验目标是利用FPGA逻辑资源，编程设计实现一个串行通用异步收发器。实验器件为“创新综合实验平台”上集成的Altera NIOSII开发板，FPGA芯片型号为EP1C12F324C8。电路设计采用VHDL硬件描述语言编程实现，开发软件为QuartusII6.0。-The goal is to use the FPGA logic resources, programming design realize a serial general asynchronous transceiver. The experiment device for "innovation comprehensive experimental platform" on integrated Altera NIOSII development board, FPGA the chip for EP1C12F324C8. Circuit design by VHDL language programming realize hardware descr iption, the development of software for the QuartusII6.0.