spi_controller/
spi_controller/bench.vcd
spi_controller/chart/
spi_controller/chart/Thumbs.db
spi_controller/chart/ͼ6-11.bmp
spi_controller/chart/ͼ6-12.bmp
spi_controller/chart/ͼ6-13.bmp
spi_controller/chart/ͼ6-14.bmp
spi_controller/chart/ͼ6-17.bmp
spi_controller/chart/ͼ6-18.bmp
spi_controller/chart/ͼ6-19.bmp
spi_controller/chart/ͼ6-7.bmp
spi_controller/spi_clgen.v
spi_controller/spi_controller.cr.mti
spi_controller/spi_controller.mpf
spi_controller/spi_defines.v
spi_controller/spi_shift.v
spi_controller/spi_slave_model.v
spi_controller/spi_top.v
spi_controller/tb_spi_top.v
spi_controller/timescale.v
spi_controller/transcript
spi_controller/vsim.wlf
spi_controller/wave/
spi_controller/wave/spi_clgen.bmp
spi_controller/wave/spi_shift.bmp
spi_controller/wave/spi_slave_model.bmp
spi_controller/wave/spi_top.bmp
spi_controller/wave/tb_spi_top.bmp
spi_controller/wave/Thumbs.db
spi_controller/wave/wb_master_model.bmp
spi_controller/wb_master_model.v
spi_controller/work/
spi_controller/work/spi_clgen/
spi_controller/work/spi_clgen/verilog.asm
spi_controller/work/spi_clgen/_primary.dat
spi_controller/work/spi_clgen/_primary.vhd
spi_controller/work/spi_shift/
spi_controller/work/spi_shift/verilog.asm
spi_controller/work/spi_shift/_primary.dat
spi_controller/work/spi_shift/_primary.vhd
spi_controller/work/spi_slave_model/
spi_controller/work/spi_slave_model/verilog.asm
spi_controller/work/spi_slave_model/_primary.dat
spi_controller/work/spi_slave_model/_primary.vhd
spi_controller/work/spi_top/
spi_controller/work/spi_top/verilog.asm
spi_controller/work/spi_top/_primary.dat
spi_controller/work/spi_top/_primary.vhd
spi_controller/work/tb_spi_top/
spi_controller/work/tb_spi_top/verilog.asm
spi_controller/work/tb_spi_top/_primary.dat
spi_controller/work/tb_spi_top/_primary.vhd
spi_controller/work/wb_master_model/
spi_controller/work/wb_master_model/verilog.asm
spi_controller/work/wb_master_model/_primary.dat
spi_controller/work/wb_master_model/_primary.vhd
spi_controller/work/_info