IIC_ISE_FPGA/automake.log
IIC_ISE_FPGA/coregen.log
IIC_ISE_FPGA/coregen.prj
IIC_ISE_FPGA/I2C.dhp
IIC_ISE_FPGA/I2C.npl
IIC_ISE_FPGA/i2c_master_bit_ctrl.cmd_log
IIC_ISE_FPGA/i2c_master_bit_ctrl.lso
IIC_ISE_FPGA/i2c_master_bit_ctrl.ngc
IIC_ISE_FPGA/i2c_master_bit_ctrl.ngr
IIC_ISE_FPGA/i2c_master_bit_ctrl.prj
IIC_ISE_FPGA/i2c_master_bit_ctrl.stx
IIC_ISE_FPGA/i2c_master_bit_ctrl.syr
IIC_ISE_FPGA/i2c_master_bit_ctrl.v
IIC_ISE_FPGA/i2c_master_bit_ctrl.v.bak
IIC_ISE_FPGA/i2c_master_bit_ctrl_vhdl.prj
IIC_ISE_FPGA/i2c_master_byte_ctrl.cmd_log
IIC_ISE_FPGA/i2c_master_byte_ctrl.lso
IIC_ISE_FPGA/i2c_master_byte_ctrl.ngc
IIC_ISE_FPGA/i2c_master_byte_ctrl.ngr
IIC_ISE_FPGA/i2c_master_byte_ctrl.prj
IIC_ISE_FPGA/i2c_master_byte_ctrl.stx
IIC_ISE_FPGA/i2c_master_byte_ctrl.syr
IIC_ISE_FPGA/i2c_master_byte_ctrl.v
IIC_ISE_FPGA/i2c_master_byte_ctrl.v.bak
IIC_ISE_FPGA/i2c_master_byte_ctrl_vhdl.prj
IIC_ISE_FPGA/i2c_master_defines.v
IIC_ISE_FPGA/i2c_master_defines.v.bak
IIC_ISE_FPGA/i2c_master_top.cmd_log
IIC_ISE_FPGA/i2c_master_top.lso
IIC_ISE_FPGA/i2c_master_top.ngc
IIC_ISE_FPGA/i2c_master_top.ngr
IIC_ISE_FPGA/i2c_master_top.prj
IIC_ISE_FPGA/i2c_master_top.stx
IIC_ISE_FPGA/i2c_master_top.syr
IIC_ISE_FPGA/i2c_master_top.v
IIC_ISE_FPGA/i2c_master_top.v.bak
IIC_ISE_FPGA/i2c_master_top_vhdl.prj
IIC_ISE_FPGA/i2c_slave_model.fdo
IIC_ISE_FPGA/i2c_slave_model.ndo
IIC_ISE_FPGA/i2c_slave_model.udo
IIC_ISE_FPGA/i2c_slave_model.v
IIC_ISE_FPGA/i2c_slave_model.v.bak
IIC_ISE_FPGA/prjname.lso
IIC_ISE_FPGA/timescale.v
IIC_ISE_FPGA/transcript
IIC_ISE_FPGA/tst_bench_top.v
IIC_ISE_FPGA/wb_master_model.v
IIC_ISE_FPGA/wb_master_model.v.bak
IIC_ISE_FPGA/work/glbl/verilog.asm
IIC_ISE_FPGA/work/glbl/_primary.dat
IIC_ISE_FPGA/work/glbl/_primary.vhd
IIC_ISE_FPGA/work/glbl
IIC_ISE_FPGA/work/i2c_slave_model/verilog.asm
IIC_ISE_FPGA/work/i2c_slave_model/_primary.dat
IIC_ISE_FPGA/work/i2c_slave_model/_primary.vhd
IIC_ISE_FPGA/work/i2c_slave_model
IIC_ISE_FPGA/work/_info
IIC_ISE_FPGA/work
IIC_ISE_FPGA/xst/work/hdllib.ref
IIC_ISE_FPGA/xst/work/vlg07/i2c_master_bit_ctrl.bin
IIC_ISE_FPGA/xst/work/vlg07
IIC_ISE_FPGA/xst/work/vlg5C/i2c_master_byte_ctrl.bin
IIC_ISE_FPGA/xst/work/vlg5C
IIC_ISE_FPGA/xst/work/vlg67/i2c_master_top.bin
IIC_ISE_FPGA/xst/work/vlg67
IIC_ISE_FPGA/xst/work
IIC_ISE_FPGA/xst
IIC_ISE_FPGA/__projnav/coregen.rsp
IIC_ISE_FPGA/__projnav/I2C.gfl
IIC_ISE_FPGA/__projnav/I2C_flowplus.gfl
IIC_ISE_FPGA/__projnav/i2c_master_bit_ctrl.xst
IIC_ISE_FPGA/__projnav/i2c_master_byte_ctrl.xst
IIC_ISE_FPGA/__projnav/i2c_master_top.xst
IIC_ISE_FPGA/__projnav/runXst_tcl.rsp
IIC_ISE_FPGA/__projnav/xst_sprjTOstx_tcl.rsp
IIC_ISE_FPGA/__projnav
IIC_ISE_FPGA/__projnav.log
IIC_ISE_FPGA