文件名称:clock1
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VHDL语言实现多功能数字钟设计：(1) 计时功能：这是本计时器设计的基本功能，每隔一分钟计时一次，并在显示屏上显示当前时间。
(2) 闹钟功能：如果当前时间与设置的闹钟时间相同，则扬声器发出蜂鸣声。
(3) 设置新的计时器时间：用户用数字键‘0’～‘9’输入新的时间，然后按 "TIME"键确认。
(4) 设置新的闹钟时间：用户用数字键“0”～“9”输入新的时间，然后按“ALARM”键确认。过程与(3)类似。
(5) 显示所设置的闹钟时间：在正常计时显示状态下，用户直接按下“ALARM”键，则已设置的闹钟时间将显示在显示屏上。
-The multi-function digital clock VHDL language design: (1) timing function: This is the basic functions of the design of the timer tick once every one minute, and the current time displayed on the screen.
(2) Alarm function: If the current time and set the alarm time, the speaker beeps.
(3) set a new timer time: use the number keys 0 to 9 to enter a new time, and then press the "TIME" button to confirm.
(4) set a new alarm time: the user to enter a new time, using the number keys "0" to "9" and then press the "ALARM" button to confirm. The process is similar to (3).
(5) set the alarm time: the normal time display, the user directly pressing the "ALARM" key already set the alarm time will be displayed on the screen.
(2) 闹钟功能：如果当前时间与设置的闹钟时间相同，则扬声器发出蜂鸣声。
(3) 设置新的计时器时间：用户用数字键‘0’～‘9’输入新的时间，然后按 "TIME"键确认。
(4) 设置新的闹钟时间：用户用数字键“0”～“9”输入新的时间，然后按“ALARM”键确认。过程与(3)类似。
(5) 显示所设置的闹钟时间：在正常计时显示状态下，用户直接按下“ALARM”键，则已设置的闹钟时间将显示在显示屏上。
-The multi-function digital clock VHDL language design: (1) timing function: This is the basic functions of the design of the timer tick once every one minute, and the current time displayed on the screen.
(2) Alarm function: If the current time and set the alarm time, the speaker beeps.
(3) set a new timer time: use the number keys 0 to 9 to enter a new time, and then press the "TIME" button to confirm.
(4) set a new alarm time: the user to enter a new time, using the number keys "0" to "9" and then press the "ALARM" button to confirm. The process is similar to (3).
(5) set the alarm time: the normal time display, the user directly pressing the "ALARM" key already set the alarm time will be displayed on the screen.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clock1/clock2.asm.rpt
clock1/clock2.done
clock1/clock2.fit.rpt
clock1/clock2.fit.smsg
clock1/clock2.fit.summary
clock1/clock2.flow.rpt
clock1/clock2.map.rpt
clock1/clock2.map.summary
clock1/clock2.pin
clock1/clock2.qpf
clock1/clock2.qsf
clock1/clock2.qws
clock1/clock2.sta.rpt
clock1/clock2.sta.summary
clock1/CONTROL.bsf
clock1/CONTROL.vhd
clock1/CONTROL.vhd.bak
clock1/COUNTER.bsf
clock1/COUNTER.vhd
clock1/COUNTER.vhd.bak
clock1/db/clock2.(0).cnf.cdb
clock1/db/clock2.(0).cnf.hdb
clock1/db/clock2.analyze_file.qmsg
clock1/db/clock2.asm.qmsg
clock1/db/clock2.cbx.xml
clock1/db/clock2.cmp.bpm
clock1/db/clock2.cmp.cdb
clock1/db/clock2.cmp.ecobp
clock1/db/clock2.cmp.hdb
clock1/db/clock2.cmp.logdb
clock1/db/clock2.cmp.rdb
clock1/db/clock2.cmp_bb.cdb
clock1/db/clock2.cmp_bb.hdb
clock1/db/clock2.cmp_bb.logdb
clock1/db/clock2.cmp_bb.rcf
clock1/db/clock2.dbp
clock1/db/clock2.db_info
clock1/db/clock2.eco.cdb
clock1/db/clock2.fit.qmsg
clock1/db/clock2.hier_info
clock1/db/clock2.hif
clock1/db/clock2.map.bpm
clock1/db/clock2.map.cdb
clock1/db/clock2.map.ecobp
clock1/db/clock2.map.hdb
clock1/db/clock2.map.logdb
clock1/db/clock2.map.qmsg
clock1/db/clock2.map_bb.cdb
clock1/db/clock2.map_bb.hdb
clock1/db/clock2.map_bb.logdb
clock1/db/clock2.pre_map.cdb
clock1/db/clock2.pre_map.hdb
clock1/db/clock2.psp
clock1/db/clock2.pss
clock1/db/clock2.rtlv.hdb
clock1/db/clock2.rtlv_sg.cdb
clock1/db/clock2.rtlv_sg_swap.cdb
clock1/db/clock2.sgdiff.cdb
clock1/db/clock2.sgdiff.hdb
clock1/db/clock2.signalprobe.cdb
clock1/db/clock2.sld_design_entry.sci
clock1/db/clock2.sld_design_entry_dsc.sci
clock1/db/clock2.sta.qmsg
clock1/db/clock2.sta.rdb
clock1/db/clock2.syn_hier_info
clock1/db/clock2.tiscmp0.ddb
clock1/db/clock2.tiscmp2.ddb
clock1/db/prev_cmp_clock2.map.qmsg
clock1/DIVIDER.bsf
clock1/DIVIDER.vhd
clock1/DIVIDER.vhd.bak
clock1/DRIVER.bsf
clock1/DRIVER.vhd
clock1/DRIVER.vhd.bak
clock1/KEYBUFFER.bsf
clock1/KEYBUFFER.vhd
clock1/KEYBUFFER.vhd.bak
clock1/Mult_Clk.vhd
clock1/prev_cmp_clock2.qmsg
clock1/P_ALARM.vhd
clock1/P_ALARM.vhd.bak
clock1/REG.bsf
clock1/REG.vhd
clock1/REG.vhd.bak
clock1/db
clock1
clock1/多功能数字钟设计.doc
clock1/clock2.done
clock1/clock2.fit.rpt
clock1/clock2.fit.smsg
clock1/clock2.fit.summary
clock1/clock2.flow.rpt
clock1/clock2.map.rpt
clock1/clock2.map.summary
clock1/clock2.pin
clock1/clock2.qpf
clock1/clock2.qsf
clock1/clock2.qws
clock1/clock2.sta.rpt
clock1/clock2.sta.summary
clock1/CONTROL.bsf
clock1/CONTROL.vhd
clock1/CONTROL.vhd.bak
clock1/COUNTER.bsf
clock1/COUNTER.vhd
clock1/COUNTER.vhd.bak
clock1/db/clock2.(0).cnf.cdb
clock1/db/clock2.(0).cnf.hdb
clock1/db/clock2.analyze_file.qmsg
clock1/db/clock2.asm.qmsg
clock1/db/clock2.cbx.xml
clock1/db/clock2.cmp.bpm
clock1/db/clock2.cmp.cdb
clock1/db/clock2.cmp.ecobp
clock1/db/clock2.cmp.hdb
clock1/db/clock2.cmp.logdb
clock1/db/clock2.cmp.rdb
clock1/db/clock2.cmp_bb.cdb
clock1/db/clock2.cmp_bb.hdb
clock1/db/clock2.cmp_bb.logdb
clock1/db/clock2.cmp_bb.rcf
clock1/db/clock2.dbp
clock1/db/clock2.db_info
clock1/db/clock2.eco.cdb
clock1/db/clock2.fit.qmsg
clock1/db/clock2.hier_info
clock1/db/clock2.hif
clock1/db/clock2.map.bpm
clock1/db/clock2.map.cdb
clock1/db/clock2.map.ecobp
clock1/db/clock2.map.hdb
clock1/db/clock2.map.logdb
clock1/db/clock2.map.qmsg
clock1/db/clock2.map_bb.cdb
clock1/db/clock2.map_bb.hdb
clock1/db/clock2.map_bb.logdb
clock1/db/clock2.pre_map.cdb
clock1/db/clock2.pre_map.hdb
clock1/db/clock2.psp
clock1/db/clock2.pss
clock1/db/clock2.rtlv.hdb
clock1/db/clock2.rtlv_sg.cdb
clock1/db/clock2.rtlv_sg_swap.cdb
clock1/db/clock2.sgdiff.cdb
clock1/db/clock2.sgdiff.hdb
clock1/db/clock2.signalprobe.cdb
clock1/db/clock2.sld_design_entry.sci
clock1/db/clock2.sld_design_entry_dsc.sci
clock1/db/clock2.sta.qmsg
clock1/db/clock2.sta.rdb
clock1/db/clock2.syn_hier_info
clock1/db/clock2.tiscmp0.ddb
clock1/db/clock2.tiscmp2.ddb
clock1/db/prev_cmp_clock2.map.qmsg
clock1/DIVIDER.bsf
clock1/DIVIDER.vhd
clock1/DIVIDER.vhd.bak
clock1/DRIVER.bsf
clock1/DRIVER.vhd
clock1/DRIVER.vhd.bak
clock1/KEYBUFFER.bsf
clock1/KEYBUFFER.vhd
clock1/KEYBUFFER.vhd.bak
clock1/Mult_Clk.vhd
clock1/prev_cmp_clock2.qmsg
clock1/P_ALARM.vhd
clock1/P_ALARM.vhd.bak
clock1/REG.bsf
clock1/REG.vhd
clock1/REG.vhd.bak
clock1/db
clock1
clock1/多功能数字钟设计.doc
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