文件名称:8259_OSED
-
所属分类:
- 标签属性:
- 上传时间:2012-11-16
-
文件大小:111.62kb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
A8259中断控制器 VHDL例程,用alteraCPLD实现,适合初学者-A8259Interrupt Controller
(系统自动生成,下载前可以参看下载内容)
下载文件列表
8259_OSED/.qsys_edit/filters.xml
8259_OSED/.qsys_edit/preferences.xml
8259_OSED/A8259 Programmable Interrupt Controller.doc
8259_OSED/A8259.csf
8259_OSED/A8259.psf
8259_OSED/A8259.quartus
8259_OSED/A8259.qws
8259_OSED/A8259.ssf
8259_OSED/Altera Reference Design License Agreement.TXT
8259_OSED/cmp_state.ini
8259_OSED/Debug.fsf
8259_OSED/readme.txt
8259_OSED/Release.fsf
8259_OSED/verilog/.xhdl/a8259
8259_OSED/verilog/.xhdl/a8259tb
8259_OSED/verilog/.xhdl/a8259top
8259_OSED/verilog/.xhdl/a8259_tst
8259_OSED/verilog/.xhdl/cwrd_reg
8259_OSED/verilog/.xhdl/initcntl
8259_OSED/verilog/.xhdl/int_ltch
8259_OSED/verilog/.xhdl/int_seq
8259_OSED/verilog/.xhdl/ir_reg
8259_OSED/verilog/.xhdl/is_reg
8259_OSED/verilog/.xhdl/ocw2_reg
8259_OSED/verilog/.xhdl/ocw3_reg
8259_OSED/verilog/.xhdl/ocw_dcde
8259_OSED/verilog/.xhdl/pri_res
8259_OSED/verilog/.xhdl/rd_mux
8259_OSED/verilog/.xhdl/rw_cntl
8259_OSED/verilog/.xhdl/seq_cntl
8259_OSED/verilog/.xhdl/vb_util
8259_OSED/verilog/.xhdl/vect_mux
8259_OSED/verilog/a8259.v
8259_OSED/verilog/a8259.vec
8259_OSED/verilog/a8259tb.v
8259_OSED/verilog/a8259top.v
8259_OSED/verilog/a8259_tst.v
8259_OSED/verilog/cwrd_reg.v
8259_OSED/verilog/initcntl.v
8259_OSED/verilog/int_ltch.v
8259_OSED/verilog/int_seq.v
8259_OSED/verilog/ir_reg.v
8259_OSED/verilog/is_reg.v
8259_OSED/verilog/ocw2_reg.v
8259_OSED/verilog/ocw3_reg.v
8259_OSED/verilog/ocw_dcde.v
8259_OSED/verilog/pri_res.v
8259_OSED/verilog/rd_mux.v
8259_OSED/verilog/rw_cntl.v
8259_OSED/verilog/seq_cntl.v
8259_OSED/verilog/vect_mux.v
8259_OSED/VHDL/.xhdl/a8259_tst
8259_OSED/VHDL/.xhdl/vb_util
8259_OSED/VHDL/A8259.VHD
8259_OSED/VHDL/A8259TB.VHD
8259_OSED/VHDL/A8259TOP.VHD
8259_OSED/VHDL/A8259_TST.VHD
8259_OSED/VHDL/CWRD_REG.VHD
8259_OSED/VHDL/INITCNTL.VHD
8259_OSED/VHDL/INT_LTCH.VHD
8259_OSED/VHDL/INT_SEQ.VHD
8259_OSED/VHDL/IR_REG.VHD
8259_OSED/VHDL/IS_REG.VHD
8259_OSED/VHDL/OCW2_REG.VHD
8259_OSED/VHDL/OCW3_REG.VHD
8259_OSED/VHDL/OCW_DCDE.VHD
8259_OSED/VHDL/PRI_RES.VHD
8259_OSED/VHDL/RD_MUX.VHD
8259_OSED/VHDL/RW_CNTL.VHD
8259_OSED/VHDL/SEQ_CNTL.VHD
8259_OSED/VHDL/VECT_MUX.VHD
8259_OSED/verilog/.xhdl
8259_OSED/VHDL/.xhdl
8259_OSED/.qsys_edit
8259_OSED/verilog
8259_OSED/VHDL
8259_OSED
8259_OSED/.qsys_edit/preferences.xml
8259_OSED/A8259 Programmable Interrupt Controller.doc
8259_OSED/A8259.csf
8259_OSED/A8259.psf
8259_OSED/A8259.quartus
8259_OSED/A8259.qws
8259_OSED/A8259.ssf
8259_OSED/Altera Reference Design License Agreement.TXT
8259_OSED/cmp_state.ini
8259_OSED/Debug.fsf
8259_OSED/readme.txt
8259_OSED/Release.fsf
8259_OSED/verilog/.xhdl/a8259
8259_OSED/verilog/.xhdl/a8259tb
8259_OSED/verilog/.xhdl/a8259top
8259_OSED/verilog/.xhdl/a8259_tst
8259_OSED/verilog/.xhdl/cwrd_reg
8259_OSED/verilog/.xhdl/initcntl
8259_OSED/verilog/.xhdl/int_ltch
8259_OSED/verilog/.xhdl/int_seq
8259_OSED/verilog/.xhdl/ir_reg
8259_OSED/verilog/.xhdl/is_reg
8259_OSED/verilog/.xhdl/ocw2_reg
8259_OSED/verilog/.xhdl/ocw3_reg
8259_OSED/verilog/.xhdl/ocw_dcde
8259_OSED/verilog/.xhdl/pri_res
8259_OSED/verilog/.xhdl/rd_mux
8259_OSED/verilog/.xhdl/rw_cntl
8259_OSED/verilog/.xhdl/seq_cntl
8259_OSED/verilog/.xhdl/vb_util
8259_OSED/verilog/.xhdl/vect_mux
8259_OSED/verilog/a8259.v
8259_OSED/verilog/a8259.vec
8259_OSED/verilog/a8259tb.v
8259_OSED/verilog/a8259top.v
8259_OSED/verilog/a8259_tst.v
8259_OSED/verilog/cwrd_reg.v
8259_OSED/verilog/initcntl.v
8259_OSED/verilog/int_ltch.v
8259_OSED/verilog/int_seq.v
8259_OSED/verilog/ir_reg.v
8259_OSED/verilog/is_reg.v
8259_OSED/verilog/ocw2_reg.v
8259_OSED/verilog/ocw3_reg.v
8259_OSED/verilog/ocw_dcde.v
8259_OSED/verilog/pri_res.v
8259_OSED/verilog/rd_mux.v
8259_OSED/verilog/rw_cntl.v
8259_OSED/verilog/seq_cntl.v
8259_OSED/verilog/vect_mux.v
8259_OSED/VHDL/.xhdl/a8259_tst
8259_OSED/VHDL/.xhdl/vb_util
8259_OSED/VHDL/A8259.VHD
8259_OSED/VHDL/A8259TB.VHD
8259_OSED/VHDL/A8259TOP.VHD
8259_OSED/VHDL/A8259_TST.VHD
8259_OSED/VHDL/CWRD_REG.VHD
8259_OSED/VHDL/INITCNTL.VHD
8259_OSED/VHDL/INT_LTCH.VHD
8259_OSED/VHDL/INT_SEQ.VHD
8259_OSED/VHDL/IR_REG.VHD
8259_OSED/VHDL/IS_REG.VHD
8259_OSED/VHDL/OCW2_REG.VHD
8259_OSED/VHDL/OCW3_REG.VHD
8259_OSED/VHDL/OCW_DCDE.VHD
8259_OSED/VHDL/PRI_RES.VHD
8259_OSED/VHDL/RD_MUX.VHD
8259_OSED/VHDL/RW_CNTL.VHD
8259_OSED/VHDL/SEQ_CNTL.VHD
8259_OSED/VHDL/VECT_MUX.VHD
8259_OSED/verilog/.xhdl
8259_OSED/VHDL/.xhdl
8259_OSED/.qsys_edit
8259_OSED/verilog
8259_OSED/VHDL
8259_OSED
1999-2046 搜珍网 All Rights Reserved.
本站作为网络服务提供者,仅为网络服务对象提供信息存储空间,仅对用户上载内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。
