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文件名称:verilog_sw_led

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2012-11-16
  • 文件大小：
    402.63kb
  • 已下载：
    0次
  • 提 供 者：
    muli*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

采用verilog编写的FPGA程序，程序的功能是按键按键消抖，quartus II 开发。芯片型号是EP2C35F484C7，时钟50MHz。-FPGA verilog to write the program, the program function is the key button is debounced, quartus II development. The chip model is EP2C35F484C7, clock 50MHz
(系统自动生成,下载前可以参看下载内容)

下载文件列表

verilog_sw_led/db/prev_cmp_verilog_sw_led.asm.qmsg
verilog_sw_led/db/prev_cmp_verilog_sw_led.eda.qmsg
verilog_sw_led/db/prev_cmp_verilog_sw_led.fit.qmsg
verilog_sw_led/db/prev_cmp_verilog_sw_led.map.qmsg
verilog_sw_led/db/prev_cmp_verilog_sw_led.qmsg
verilog_sw_led/db/prev_cmp_verilog_sw_led.tan.qmsg
verilog_sw_led/db/verilog_sw_led.(0).cnf.cdb
verilog_sw_led/db/verilog_sw_led.(0).cnf.hdb
verilog_sw_led/db/verilog_sw_led.asm.qmsg
verilog_sw_led/db/verilog_sw_led.asm_labs.ddb
verilog_sw_led/db/verilog_sw_led.cbx.xml
verilog_sw_led/db/verilog_sw_led.cmp.bpm
verilog_sw_led/db/verilog_sw_led.cmp.cdb
verilog_sw_led/db/verilog_sw_led.cmp.ecobp
verilog_sw_led/db/verilog_sw_led.cmp.hdb
verilog_sw_led/db/verilog_sw_led.cmp.kpt
verilog_sw_led/db/verilog_sw_led.cmp.logdb
verilog_sw_led/db/verilog_sw_led.cmp.rdb
verilog_sw_led/db/verilog_sw_led.cmp.tdb
verilog_sw_led/db/verilog_sw_led.cmp0.ddb
verilog_sw_led/db/verilog_sw_led.cmp2.ddb
verilog_sw_led/db/verilog_sw_led.cmp_merge.kpt
verilog_sw_led/db/verilog_sw_led.db_info
verilog_sw_led/db/verilog_sw_led.eco.cdb
verilog_sw_led/db/verilog_sw_led.eda.qmsg
verilog_sw_led/db/verilog_sw_led.fit.qmsg
verilog_sw_led/db/verilog_sw_led.hier_info
verilog_sw_led/db/verilog_sw_led.hif
verilog_sw_led/db/verilog_sw_led.lpc.html
verilog_sw_led/db/verilog_sw_led.lpc.rdb
verilog_sw_led/db/verilog_sw_led.lpc.txt
verilog_sw_led/db/verilog_sw_led.map.bpm
verilog_sw_led/db/verilog_sw_led.map.cdb
verilog_sw_led/db/verilog_sw_led.map.ecobp
verilog_sw_led/db/verilog_sw_led.map.hdb
verilog_sw_led/db/verilog_sw_led.map.kpt
verilog_sw_led/db/verilog_sw_led.map.logdb
verilog_sw_led/db/verilog_sw_led.map.qmsg
verilog_sw_led/db/verilog_sw_led.map_bb.cdb
verilog_sw_led/db/verilog_sw_led.map_bb.hdb
verilog_sw_led/db/verilog_sw_led.map_bb.logdb
verilog_sw_led/db/verilog_sw_led.pre_map.cdb
verilog_sw_led/db/verilog_sw_led.pre_map.hdb
verilog_sw_led/db/verilog_sw_led.rtlv.hdb
verilog_sw_led/db/verilog_sw_led.rtlv_sg.cdb
verilog_sw_led/db/verilog_sw_led.rtlv_sg_swap.cdb
verilog_sw_led/db/verilog_sw_led.sgdiff.cdb
verilog_sw_led/db/verilog_sw_led.sgdiff.hdb
verilog_sw_led/db/verilog_sw_led.sld_design_entry.sci
verilog_sw_led/db/verilog_sw_led.sld_design_entry_dsc.sci
verilog_sw_led/db/verilog_sw_led.syn_hier_info
verilog_sw_led/db/verilog_sw_led.tan.qmsg
verilog_sw_led/db/verilog_sw_led.tis_db_list.ddb
verilog_sw_led/db/verilog_sw_led.tmw_info
verilog_sw_led/db/wed.wsf
verilog_sw_led/incremental_db/compiled_partitions/verilog_sw_led.root_partition.cmp.atm
verilog_sw_led/incremental_db/compiled_partitions/verilog_sw_led.root_partition.cmp.dfp
verilog_sw_led/incremental_db/compiled_partitions/verilog_sw_led.root_partition.cmp.hdbx
verilog_sw_led/incremental_db/compiled_partitions/verilog_sw_led.root_partition.cmp.kpt
verilog_sw_led/incremental_db/compiled_partitions/verilog_sw_led.root_partition.cmp.logdb
verilog_sw_led/incremental_db/compiled_partitions/verilog_sw_led.root_partition.cmp.rcf
verilog_sw_led/incremental_db/compiled_partitions/verilog_sw_led.root_partition.map.atm
verilog_sw_led/incremental_db/compiled_partitions/verilog_sw_led.root_partition.map.dpi
verilog_sw_led/incremental_db/compiled_partitions/verilog_sw_led.root_partition.map.hdbx
verilog_sw_led/incremental_db/compiled_partitions/verilog_sw_led.root_partition.map.kpt
verilog_sw_led/incremental_db/README
verilog_sw_led/simulation/modelsim/modelsim.ini
verilog_sw_led/simulation/modelsim/msim_transcript
verilog_sw_led/simulation/modelsim/rtl_work/verilog_sw_led/verilog.prw
verilog_sw_led/simulation/modelsim/rtl_work/verilog_sw_led/verilog.psm
verilog_sw_led/simulation/modelsim/rtl_work/verilog_sw_led/_primary.dat
verilog_sw_led/simulation/modelsim/rtl_work/verilog_sw_led/_primary.dbs
verilog_sw_led/simulation/modelsim/rtl_work/verilog_sw_led/_primary.vhd
verilog_sw_led/simulation/modelsim/rtl_work/verilog_sw_led_vlg_tst/verilog.prw
verilog_sw_led/simulation/modelsim/rtl_work/verilog_sw_led_vlg_tst/verilog.psm
verilog_sw_led/simulation/modelsim/rtl_work/verilog_sw_led_vlg_tst/_primary.dat
verilog_sw_led/simulation/modelsim/rtl_work/verilog_sw_led_vlg_tst/_primary.dbs
verilog_sw_led/simulation/modelsim/rtl_work/verilog_sw_led_vlg_tst/_primary.vhd
verilog_sw_led/simulation/modelsim/rtl_work/_info
verilog_sw_led/simulation/modelsim/rtl_work/_vmake
verilog_sw_led/simulation/modelsim/verilog_sw_led.sft
verilog_sw_led/simulation/modelsim/verilog_sw_led.vo
verilog_sw_led/simulation/modelsim/verilog_sw_led.vt
verilog_sw_led/simulation/modelsim/verilog_sw_led.vt.bak
verilog_sw_led/simulation/modelsim/verilog_sw_led.vwf
verilog_sw_led/simulation/modelsim/verilog_sw_led_modelsim.xrf
verilog_sw_led/simulation/modelsim/verilog_sw_led_run_msim_rtl_verilog.do
verilog_sw_led/simulation/modelsim/verilog_sw_led_run_msim_rtl_verilog.do.bak
verilog_sw_led/simulation/modelsim/verilog_sw_led_run_msim_rtl_verilog.do.bak1
verilog_sw_led/simulation/modelsim/verilog_sw_led_run_msim_rtl_verilog.do.bak2
verilog_sw_led/simulation/modelsim/verilog_sw_led_v.sdo
verilog_sw_led/verilog_sw_led.asm.rpt
verilog_sw_led/verilog_sw_led.done
verilog_sw_led/verilog_sw_led.dpf
verilog_sw_led/verilog_

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