This paper presents several low-latency mixed-timing

FIFO (first-in–first-out) interfaces designs that interface systems

on a chip working at different speeds. The connected systems

can be either synchronous or asynchronous. The designs are then

adapted to work between systems with very long interconnect

delays, by migrating a single-clock solution by Carloni et al.

(1999, 2000, and 2001) (for “latency-insensitive” protocols) to

mixed-timing domains. The new designs can be made arbitrarily

robust with regard to metastability and interface operating speeds.

Initial simulations for both latency and throughput are promising.