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文件名称:Static-PLL

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.46mb
  • 已下载：
    0次
  • 提 供 者：
    林****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于Actel开发平台的静态锁相环设计，verilog实现-Actel development platform based on the static PLL design, verilog realized
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Static PLL/Static PLL实验例程.pdf
Static PLL/Static_PLL_lab.rar
Static PLL/Stc_PLL/designer/impl1/designer.log
Static PLL/Stc_PLL/designer/impl1/designer_gen_ba.log
Static PLL/Stc_PLL/designer/impl1/designer_synth_check.log
Static PLL/Stc_PLL/designer/impl1/flashpro.log
Static PLL/Stc_PLL/designer/impl1/PLL_top.adb
Static PLL/Stc_PLL/designer/impl1/PLL_top.dtf/PLL_top/$$FlashPro_FPBBALTLPT1.L$$
Static PLL/Stc_PLL/designer/impl1/PLL_top.dtf/PLL_top/PLL_top.log
Static PLL/Stc_PLL/designer/impl1/PLL_top.dtf/PLL_top/PLL_top.pro
Static PLL/Stc_PLL/designer/impl1/PLL_top.dtf/PLL_top/projectData/PLL_top.stp
Static PLL/Stc_PLL/designer/impl1/PLL_top.dtf/verify.log
Static PLL/Stc_PLL/designer/impl1/PLL_top.ide_des
Static PLL/Stc_PLL/designer/impl1/PLL_top.pdb
Static PLL/Stc_PLL/designer/impl1/PLL_top.pdb.depends
Static PLL/Stc_PLL/designer/impl1/PLL_top.stp
Static PLL/Stc_PLL/designer/impl1/PLL_top.tcl
Static PLL/Stc_PLL/designer/impl1/PLL_top_1.adb
Static PLL/Stc_PLL/designer/impl1/PLL_top_1.ide_des
Static PLL/Stc_PLL/designer/impl1/PLL_top_ba.sdf
Static PLL/Stc_PLL/designer/impl1/PLL_top_ba.v
Static PLL/Stc_PLL/designer/impl1/Static_PLL.ide_des
Static PLL/Stc_PLL/hdl/ctrl_PLL.v
Static PLL/Stc_PLL/hdl/hdlsynchk.tcl
Static PLL/Stc_PLL/hdl/PLL_top.v
Static PLL/Stc_PLL/simulation/meminit.dat
Static PLL/Stc_PLL/simulation/modelsim.ini
Static PLL/Stc_PLL/simulation/modelsim.ini.sav
Static PLL/Stc_PLL/simulation/modelsim.log
Static PLL/Stc_PLL/simulation/presynth/@p@l@l_top/verilog.psm
Static PLL/Stc_PLL/simulation/presynth/@p@l@l_top/_primary.dat
Static PLL/Stc_PLL/simulation/presynth/@p@l@l_top/_primary.vhd
Static PLL/Stc_PLL/simulation/presynth/@static_@p@l@l/verilog.psm
Static PLL/Stc_PLL/simulation/presynth/@static_@p@l@l/_primary.dat
Static PLL/Stc_PLL/simulation/presynth/@static_@p@l@l/_primary.vhd
Static PLL/Stc_PLL/simulation/presynth/ctrl_@p@l@l/verilog.psm
Static PLL/Stc_PLL/simulation/presynth/ctrl_@p@l@l/_primary.dat
Static PLL/Stc_PLL/simulation/presynth/ctrl_@p@l@l/_primary.vhd
Static PLL/Stc_PLL/simulation/presynth/stimulus/verilog.psm
Static PLL/Stc_PLL/simulation/presynth/stimulus/_primary.dat
Static PLL/Stc_PLL/simulation/presynth/stimulus/_primary.vhd
Static PLL/Stc_PLL/simulation/presynth/tb_clock_minmax/verilog.psm
Static PLL/Stc_PLL/simulation/presynth/tb_clock_minmax/_primary.dat
Static PLL/Stc_PLL/simulation/presynth/tb_clock_minmax/_primary.vhd
Static PLL/Stc_PLL/simulation/presynth/testbench/verilog.psm
Static PLL/Stc_PLL/simulation/presynth/testbench/_primary.dat
Static PLL/Stc_PLL/simulation/presynth/testbench/_primary.vhd
Static PLL/Stc_PLL/simulation/presynth/_info
Static PLL/Stc_PLL/simulation/run.do
Static PLL/Stc_PLL/simulation/vsim.wlf
Static PLL/Stc_PLL/simulation/wave.do
Static PLL/Stc_PLL/smartgen/smartgen.aws
Static PLL/Stc_PLL/smartgen/Static_PLL/Static_PLL.cxf
Static PLL/Stc_PLL/smartgen/Static_PLL/Static_PLL.gen
Static PLL/Stc_PLL/smartgen/Static_PLL/Static_PLL.log
Static PLL/Stc_PLL/smartgen/Static_PLL/Static_PLL.v
Static PLL/Stc_PLL/smartgen/Static_PLL_work.ixf
Static PLL/Stc_PLL/Stc_PLL.prj
Static PLL/Stc_PLL/stimulus/BtimErrors.log
Static PLL/Stc_PLL/stimulus/files_to_build.txt
Static PLL/Stc_PLL/stimulus/PLL_top.dsk
Static PLL/Stc_PLL/stimulus/PLL_top.hpj
Static PLL/Stc_PLL/stimulus/PLL_top_tbench.bk
Static PLL/Stc_PLL/stimulus/PLL_top_tbench.btim
Static PLL/Stc_PLL/stimulus/PLL_top_tbench.v
Static PLL/Stc_PLL/stimulus/waveperl.log
Static PLL/Stc_PLL/synthesis/.recordref
Static PLL/Stc_PLL/synthesis/dm/PLL_top_1.xdm
Static PLL/Stc_PLL/synthesis/identify.log
Static PLL/Stc_PLL/synthesis/PLL_top.areasrr
Static PLL/Stc_PLL/synthesis/PLL_top.edn
Static PLL/Stc_PLL/synthesis/PLL_top.fse
Static PLL/Stc_PLL/synthesis/PLL_top.htm
Static PLL/Stc_PLL/synthesis/PLL_top.map
Static PLL/Stc_PLL/synthesis/PLL_top.sap
Static PLL/Stc_PLL/synthesis/PLL_top.sdf
Static PLL/Stc_PLL/synthesis/PLL_top.srd
Static PLL/Stc_PLL/synthesis/PLL_top.srm
Static PLL/Stc_PLL/synthesis/PLL_top.srr
Static PLL/Stc_PLL/synthesis/PLL_top.srs
Static PLL/Stc_PLL/synthesis/PLL_top.tlg
Static PLL/Stc_PLL/synthesis/PLL_top_1.areasrr
Static PLL/Stc_PLL/synthesis/PLL_top_1.edn
Static PLL/Stc_PLL/synthesis/PLL_top_1.fse
Static PLL/Stc_PLL/synthesis/PLL_top_1.htm
Static PLL/Stc_PLL/synthesis/PLL_top_1.map
Static PLL/Stc_PLL/synthesis/PLL_top_1.pdc
Static PLL/Stc_PLL/synthesis/PLL_top_1.sdf
Static PLL/Stc_PLL/synthesis/PLL_top_1.so
Static PLL/Stc_PLL/synthesis/PLL_top_1.srd
Static PLL/Stc_PLL/synthesis/PLL_top_1.srl
Static PLL/Stc_PLL/synthesis/PLL_top_1.srm
Static PLL/Stc_PLL/synthesis/PLL_top_1.srr
Static PLL/Stc_PLL/synthesis/PLL_top_1.srs
Static PLL/Stc_PLL/synthesis/PLL_top_1.szr
Static PLL/Stc_PLL/synthesis/PLL_top_1.tlg
Static PLL/Stc_PLL/synthesis/PLL_top_1.v
Static PLL/Stc_PLL/synthesis/PLL_top_1_sdc.sdc
Static PLL/Stc_PLL/synthesis/PLL_top_sdc.sdc
Static PLL/Stc_PLL/synthesis/PLL_top_syn.prj
Static PLL/Stc_PLL/synthesis/run_options.txt
Static PLL/Stc_PLL/synthesis/scratchproject.prs
Static PLL/Stc_PLL/synthesis/stdout.log
Static PLL/Stc_PLL/synthesis/synlog/PLL_top_1_ProASIC3_Mapper.srr
Static PLL/Stc_PLL/synthesis/synlog/PLL_top_1_Pr

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