文件名称:TCOLLOR_CHAR_h
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- 上传时间：2012-11-16
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文件大小：485.31kb
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此ip核是xvga视频接口控制器，，主要针对xilinx公司的开发工具
-This IP core is the xvga video interface controller, the main development tool for xilinx
-This IP core is the xvga video interface controller, the main development tool for xilinx
(系统自动生成,下载前可以参看下载内容)
下载文件列表
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/data/COLOR_CHAR_MODE_SVGA_CTRL_v2_1_0.bbd
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/data/COLOR_CHAR_MODE_SVGA_CTRL_v2_1_0.mpd
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/data/COLOR_CHAR_MODE_SVGA_CTRL_v2_1_0.pao
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/doc/ASCII CODE MAP.PDF
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/CHARACTER_MODE.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/CHAR_GEN_ROM.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/CHAR_RAM.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/CLOCKGEN.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/CLUT.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/COLOR_CHAR_MODE_SVGA_CTRL.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/COLOR_PIPE.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/COLOR_RAM.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/DRIVE_DAC_DATA.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/AutoConstraint_COLOR_CHAR_MODE_SVGA_CTRL.sdc
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.edf
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.fse
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.ncf
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.srd
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.srm
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.srr
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.srs
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.tlg
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/syntmp/COLOR_CHAR_MODE_SVGA_CTRL.plg
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/svga_defines.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/SVGA_TIMING_GENERATION.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/TEST_COLOR_CHAR_MODE.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/vga_video.prd
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/vga_video.prj
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.edf
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.fse
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.ncf
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.srd
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.srm
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.srr
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.srs
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.tlg
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/syntmp/COLOR_CHAR_MODE_SVGA_CTRL.plg
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/syntmp
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/syntmp
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/data
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/doc
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b
TCOLLOR_CHAR_h
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/data/COLOR_CHAR_MODE_SVGA_CTRL_v2_1_0.mpd
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/data/COLOR_CHAR_MODE_SVGA_CTRL_v2_1_0.pao
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/doc/ASCII CODE MAP.PDF
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/CHARACTER_MODE.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/CHAR_GEN_ROM.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/CHAR_RAM.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/CLOCKGEN.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/CLUT.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/COLOR_CHAR_MODE_SVGA_CTRL.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/COLOR_PIPE.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/COLOR_RAM.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/DRIVE_DAC_DATA.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/AutoConstraint_COLOR_CHAR_MODE_SVGA_CTRL.sdc
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.edf
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.fse
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.ncf
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.srd
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.srm
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.srr
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.srs
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/COLOR_CHAR_MODE_SVGA_CTRL.tlg
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/syntmp/COLOR_CHAR_MODE_SVGA_CTRL.plg
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/svga_defines.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/SVGA_TIMING_GENERATION.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/TEST_COLOR_CHAR_MODE.v
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/vga_video.prd
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/vga_video.prj
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.edf
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.fse
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.ncf
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.srd
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.srm
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.srr
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.srs
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/COLOR_CHAR_MODE_SVGA_CTRL.tlg
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/syntmp/COLOR_CHAR_MODE_SVGA_CTRL.plg
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1/syntmp
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog/rev_1
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl/verilog
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist/syntmp
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/data
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/doc
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/hdl
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b/netlist
TCOLLOR_CHAR_h/COLOR_CHAR_MODE_SVGA_CTRL_v1_00_b
TCOLLOR_CHAR_h
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